Fabricating and operating a memory array having a multi-level cell region and a single-level cell region
AssigneeSanDisk Technologies LLC
InventorsFumitoshi Ito, Shinji Sato
Life of this patent
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Abstract
Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.
Claims34
A non-volatile storage system, comprising:
- a memory array having a first region including a first plurality of non-volatile storage elements having source drain regions having a first concentration of ions, the non-volatile storage elements in the first region having a second concentration of ions near the source/drain regions, the conductivity type of the first concentration is opposite the conductivity type of the second concentration;
- the memory array having a second region including a second plurality of non-volatile storage elements having source drain regions having a third concentration of ions, the non-volatile storage elements in the second region having a fourth concentration of zero or more ions near the source/drain regions, either the first concentration of ions is less than the third concentration of ions or the second concentration of ions is greater than the fourth concentration of ions.
A method of forming a memory array of non-volatile storage elements, the method comprising:
- forming a first region including a first plurality of floating gate stacks above a substrate, the first region is for multi-level non-volatile storage elements;
- forming a second region including a second plurality of floating gate stacks above the substrate, the second region is for single-level non-volatile storage elements;
- implanting ions having a first concentration in the substrate for source/drain regions in the first region;
- implanting ions having a second concentration in the substrate near the source/drain regions in the first region, the conductivity type of the first concentration of ions is opposite the conductivity type of the second concentration of ions;
- implanting a third concentration of ions in the substrate for source/drain regions in the second region;
- and
- implanting a fourth concentration of zero or more ions in the substrate near the source/drain regions in the second region, either the first concentration is less than the third concentration or the second concentration is greater than the fourth concentration.
A non-volatile storage system, comprising:
- a first plurality of NAND strings of non-volatile storage elements in a first region of a memory array, the first region is for multi-level non-volatile storage elements;
- a second plurality of NAND strings of non-volatile storage elements in a second region of the memory array, the second region is for single-level non-volatile storage elements;
- first shallow trench isolation structures that separate adjacent ones of the first plurality of NAND strings;
- and
- second shallow trench isolation structures that separate adjacent ones of the second plurality of NAND strings, the first shallow trench isolation structures have a deep etch back and the second shallow trench isolation structures have a shallow etch back.
A method of forming a memory array of non-volatile storage elements, the method comprising:
- forming a first region including a first plurality of polysilicon strips to be used to form first floating gates above a substrate, the first region is for multi-level non-volatile storage elements;
- forming a second region including a second plurality of polysilicon strips to be used to form second floating gates above the substrate, the second region is for single-level non-volatile storage elements;
- depositing isolation material between adjacent ones of the first plurality of polysilicon strips and between adjacent ones of the second plurality of polysilicon strips;
- performing a shallow etch back of the isolation material in the second region;
- and
- performing a deep etch back of the isolation material in the first region.
A non-volatile storage system, comprising:
- a group of non-volatile storage elements associated with a bit line;
- and
- one or more managing circuits in communication with the group of non-volatile storage elements, the one or more managing circuits reads the group of non-volatile storage elements during a first period by applying a first voltage to the bit line, the first period is associated with less than a threshold amount of use, the one or more managing circuits reads the group of non-volatile storage elements during a second period by applying a second voltage to the bit line, the second period is associated with more than the threshold amount of use.
A method for operating non-volatile storage, comprising:
- reading a group of non-volatile storage elements associated with a bit line during a first period by applying a first voltage to the bit line, the first period is associated with less than a threshold amount of use;
- and
- reading the group of non-volatile storage elements during a second period by applying a second voltage to the bit line, the second period is associated with more than the threshold amount of use.
Dependencies are inferred from the claim text.