Loading patent…
AssigneeSamsung Electronics Co., Ltd.
InventorsBEAK-HYUNG CHO, Do-Eung Kim, Choong-Keun Kwak, Sang-Beom Kang, Woo-Yeong Cho, Hyung-Rok Oh
Estimating the term…
A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines; a bias circuit for biasing a selected second line of the second lines to a reference voltage and a non-selected second line to a first voltage; and a local word line address decoder applying the reference voltage or a pumping voltage corresponding to the first voltage to the bias circuit.
A semiconductor memory device comprising:
A method of writing data to a selected memory cell connected to a selected first line and a selected second line of a semiconductor memory device including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line of a plurality of first lines and a second terminal of the memory cell is connected to a corresponding second line of a plurality of second lines, the method comprising:
A semiconductor memory device, comprising:
A semiconductor memory device comprising:
Dependencies are inferred from the claim text.