Memory device, memory system having the same, and programming method of a memory cell
AssigneeSamsung Electronics Co., Ltd.
InventorsHo-Jung Kim, Sang-Beom Kang, Chul Woo Park, Hyun Ho Choi
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell.
Claims32
A method of writing data to a nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, the method comprising:
- writing a least significant bit for each multi-level memory cell of the plurality of memory cells;
- and
- after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell.
A multi-level non-volatile memory device, comprising:
- a plurality of multi-level memory cells, the plurality being at least two;
- and
- a controller configured to write a least significant bit for each multi-level memory cell of the plurality of multi-level memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of multi-level memory cells, to write a next significant bit for each multi-level memory cell.
A system, comprising:
- a processor;
- and
- a multi-level non-volatile memory device, including:
- a plurality of multi-level memory cells, the plurality being at least two;
- and
- a controller configured to write a least significant bit for each multi-level memory cell of the plurality of multi-level memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, to write a next significant bit for each multi-level memory cell.
Dependencies are inferred from the claim text.