Flip-chip fet cell
AssigneeViaSat, Inc.
InventorKenneth V. Buer
Life of this patent
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Abstract
A method and system for a FET cell is presented. The FET cell includes multiple individual transistors and interconnect bumps that are configured to flip-chip connect to a substrate. The substrate may have the majority of a matching structure for the FET cell. Furthermore, the FET cell may include a stability circuit in communication with the terminals of the individual transistors and further in communication with the interconnect bumps. Additionally, different materials can be used in combination in the FET cell and the separate substrate having the majority of the matching structure. Various materials may be more efficiency used in a FET cell, while other materials are suitable for the separate substrate.
Claims23
A field effect transistor (FET) cell comprising:
- a plurality of individual transistors located on a first substrate;
- a plurality of interconnect bumps configured to flip-chip connect the FET cell to a second substrate;
- and
- a stability circuit in communication with terminals of the plurality of individual transistors and further in communication with the plurality of interconnect bumps.
A power amplifier comprising:
- a substrate;
- at least one FET cell coupled to the substrate and having an RF input and an RF output, the RF output in communication with a matching structure, wherein at least a portion of the matching structure is on the substrate, and wherein the at least one FET cell comprises two or more transistors;
- and
- a flip-chip connection for electrically connecting the at least one FET cell to the substrate.
An electronic system comprising:
- a FET cell further comprising;
- a plurality of FETs;
- a gate interconnect bump;
- a source interconnect bump;
- a drain interconnect bump;
- and
- a substrate comprising a matching structure corresponding to the FET cell;
- wherein the FET cell is flip-chip connected to the substrate.
A power amplifier comprising:
- at least two FET cells connected to a substrate by flip-chip techniques, wherein the at least two FET cells further comprise interconnect bumps configured to facilitate the flip-chip techniques;
- wherein the substrate further comprises matching structure related to a plurality of FETs on the at least two FET cells, and wherein each of the at least two FET cells further comprise stabilization circuitry and DC blocking circuitry.
Dependencies are inferred from the claim text.