Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus

A method of driving a solid-state imaging device, the solid-state imaging device including a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of received light, and a plurality of MOS transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to the pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels,

• the method comprising steps of:
• starting concurrently an exposure operation on all the pixels, stopping concurrently the exposure operation on all the pixels, and then reading onto charge storage capacitance units the signal charges generated on the light sensing units of the pixels;
• and
• inputting a drive pulse to a predetermined pixel from the pixel drive circuit arranged beneath the predetermined pixel and outputting as the pixel signal the signal charge stored on the charge storage capacitance unit of the predetermined pixel.

An electronic apparatus, comprising:

• an optical lens;
• a solid-state imaging device, the solid-state imaging device including a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of light received through the optical lens, and a plurality of MOS transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to the pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels;
• and
• a signal processing circuit for processing a signal output from the solid-state imaging device.

A solid-state imaging device, comprising:

• a first chip including a cyclic layout pattern circuit having unit circuits cyclically arranged in a regular pattern in at least one of a row direction along which rows of pixels of a pixel array having a matrix of rows and columns of pixels, each pixel including a photoelectric converter, are arranged, and a column direction along which columns of pixels of the pixel array are arranged;
• a second chip laminated on the first chip, the second chip including an adjustment circuit for adjusting individually a timing of a signal of each unit circuit of the cyclic layout pattern circuit, the adjustment circuit including a storage unit and a plurality of unit circuits corresponding to the unit circuits of the cyclic layout pattern circuit;
• and
• a connection unit, having a three-dimensional connection structure, for electrically connecting each unit circuit of the cyclic layout pattern on the first chip to each unit circuit of the adjustment circuit on the second chip in a mapped relationship.

An electronic apparatus comprising a solid-state imaging device, the solid-state imaging device including:

• a first chip including a cyclic layout pattern circuit having unit circuits cyclically arranged in a regular pattern in at least one of a row direction along which rows of pixels of a pixel array having a matrix of rows and columns of pixels, each pixel including a photoelectric converter, run, and a column direction along which columns of pixels of the pixel array run;
• a second chip laminated on the first chip, the second chip including an adjustment circuit for adjusting individually a timing of a signal of each unit circuit of the cyclic layout pattern circuit, the adjustment circuit including a storage unit and a plurality of unit circuits corresponding to the unit circuits of the cyclic layout pattern circuit;
• and
• a connection unit for electrically connecting each unit circuit of the cyclic layout pattern to each unit circuit of the adjustment circuit in a mapped relationship.