Hardware implemented pixel level digital filter and processing of electromagnetic signals

The apparatus of claim 1, 2, 3 and 4 for performing digital video target detection of a sequence of raster input pixel signals, each respective raster input pixel having, an ordered n-tuple set of values from a video camera or sensors to signify n-tuple sub-bands (channels) of IR electromagnetic wavelengths, the apparatus consisting of the following:

• a) a digital video synchronization and timing that synchronizes to the header of the incoming digital video data bit stream and provides digital timing and control signal required to identify each one of the “n” tuple set of prime colors, and position of each prime color within a pixel timing;
• b) digital filter memories, coupled to receive the intensities of the n-topple sequence of raster input sub-band signal intensities and map each respective n-topple intensity into a respective sub-band memory address each memory address having:
• a predetermined memory address range,
• a sub-band identity number of,
• a group of sub bands spectra and prime colors belonging to an object within as;
• a multi sub-band object's group identity number;
• identification of a sub-band of an object within a group of sub-bands belonging to an object, and within different groups of sub-bands;
• preloaded with a single bit markers at predetermined addresses;
• single bit markers addresses representing a band pass, low pass or high pass filters to be addressed by intensities intended to be detected as a band of filters (“0” not detect, and “1” for detect);
• c) sub-band identification marks are input to an n-input AND gate to represent simultaneous detection of all the sub-bands within a pixel timing to declare detections of targets in diffident spectra.

The apparatus of claims 1 and 5 further providing statistical accumulations of detected pixels of each channel in a multi frame memory in which each channel is dedicated to one of the bits within memory data bit patterns to represent total number of detections of that channel within an arbitrary “f” number of frames and each memory address corresponds to the pixel coordinates in a frame as follows:

• a) a set of registers, initialized by a frame header synchronization logic, that is maintained to represent the row and column coordinates of pixel address within a frame of video data that is used to address memories;
• b) a set of dual registers A, and B to hold channels detect no detect signals from one pixel timing to the next, to be written into a memory;
• c) a set of dual memory frames of A, and B representing the statistical detection occurrences of detected intensities of pixels in one frame;
• d) a set of dual memory frames of A, and B representing the statistical detection occurrences of detected intensities of pixels in “f” number of frames;
• e) a set of timing generators signifying different timing within a pixel data bit stream period to provide necessary timing to read the contents (partial) of the memory increment the data and write the incremented data back to the memory for “f” number of frames;
• f) a set of FIFO's to write the detect no detect of a multiform accumulations of each channel along with the pixel addresses for further processing.

An apparatus to generate memory address to a large memory system and memory banks in which the source of address generation is plurality of “n” registers, each register is set to different variable values of n(1), n(2), n(3), to n(x), wherein x denotes the length of each register, the apparatus consisting of the following:

• a) plurality of “n” registers, each register receiving its data from different sources, of sensors or CPU;
• b) a memory based address lookup table, coupled to the registers, to translate variable data into a fixed memory address;
• the memory based lookup table, is either a PROM or a Random Access Memory, wherein the contents of the RAM is set by a register or CPU, to address lookup table generates memory bank address, and memory address;
• the address lookup table provides a translation from all the various levels of strength (quotient), to an absolute memory bank address value, within a memory bank;
• an address lookup table provides a translation from a set of pre assigned variable levels of strength and direct inputs from the computer address latch, to an absolute memory bank address value, for selecting a memory bank;
• c) a set of memory banks addressed by the selected registers or memory address lookup table;
• each bank consisting of a sub-bank memory selector, Data Memory Selector and instruction memories;
• instruction memories preloaded with application instruction relevant to the register settings and feedback instruction registers;
• Instructions fed to the CPU through a FIFO to execute specific instructions related to register settings;
• each instruction containing executable instructions, a feedback (to the registers) data, and a number relating to the instruction bytes to be followed;
• d) A CPU receiving information specified in the above through a FIFO for necessary executions with an option to load feedback instruction either before or after the execution of instructions.
• e) a feedback generator