Lcd electrode arrangement

A device comprising:

• a processor;
• a memory device operably coupled to the processor and configured to store video data;
• and
• a liquid crystal display configured to display the video data by one video frame at a time, the liquid crystal display having a pixel array including rows and columns of pixels, each pixel including:
• a pixel electrode;
• a common electrode configured to generate an electric field in conjunction with the pixel electrode;
• a portion of a dielectric passivation layer shared by the pixels of the pixel array, wherein the portion of the dielectric passivation layer is disposed between the pixel electrode and the common electrode;
• and
• a transistor having a gate connected to one of a plurality of gate lines of the pixel array and a source connected to one of a plurality of data lines of the pixel array, wherein the transistor is configured to provide a data signal from the source line to the pixel electrode when a scanning signal is received on the gate line;
• wherein the pixels of each row of the pixel array are configured to cause a neutral amount of direct current bias on the dielectric passivation layer when the pixels of each row of the pixel array receive a scanning signal and a data signal.

A display panel comprising:

• a pixel array including rows and columns of pixels, each pixel including:
• an upper electrode;
• a portion of a dielectric layer shared by a plurality of pixels, wherein the portion of the dielectric layer is disposed beneath the upper electrode;
• a lower electrode disposed beneath the portion of the dielectric layer;
• and
• a transistor configured to provide a data signal from a data line to one of either the upper electrode or the lower electrode when the transistor is activated;
• wherein the upper electrode of the pixel is configured to receive a common voltage when the transistor is configured to provide the data signal to the lower electrode and wherein the lower electrode is configured to receive the common voltage when the transistor is configured to provide the data signal to the upper electrode;
• wherein the transistor of a first pixel of the pixel array is configured to provide the data signal to the upper electrode of the first pixel and wherein the transistor of a second pixel of the pixel array is configured to provide the data signal to the lower electrode of the second pixel.

A method of controlling a liquid crystal display comprising:

• supplying a common voltage of a first polarity to common electrodes of pixels of even-numbered rows of a pixel array, wherein the common electrodes of a first plurality of the pixels of the even-numbered rows are disposed above respective pixel electrodes of the first plurality of pixels of the even-numbered rows and wherein the common electrodes of a second plurality of the pixels of the even-numbered rows are disposed above respective pixel electrodes of the second plurality of pixels of the even-numbered rows;
• supplying a common voltage of a second polarity to common electrodes of pixels of odd-numbered rows of a pixel array, wherein the common electrodes of a first plurality of the pixels of the odd-numbered rows are disposed above respective pixel electrodes of the first plurality of pixels of the odd-numbered rows and wherein the common electrodes of a second plurality of the pixels of the odd-numbered rows are disposed above respective pixel electrodes of the second plurality of pixels of the odd-numbered rows;
• and
• activating each row of pixels of the pixel array one at a time until all rows have been activated for a first video frame.