Wideband jammer detector

A peak detector block including a transistor, a capacitor circuit, and a comparator circuit where:

• a gate terminal of the transistor is coupled to an input signal,
• a source terminal of the transistor is coupled to a power source,
• a drain terminal of the transistor is coupled to a first terminal of the capacitor circuit and an input terminal of the comparator circuit, and
• a second terminal of the capacitor circuit is coupled to a ground signal source.

A peak detector block including a first transistor, a second transistor, a first capacitor, a second capacitor and a comparator circuit, where:

• a gate terminal of the first transistor is coupled to an input signal,
• a source terminal of the first transistor is coupled to a first power source,
• a drain terminal of the first transistor is coupled to a first terminal of the first capacitor and a first input terminal of the comparator circuit,
• a second terminal of the first capacitor is coupled to a ground signal source,
• a gate terminal of the second transistor is coupled to the input signal,
• a source terminal of the second transistor is coupled to a second power source,
• a drain terminal of the second transistor is coupled to a first terminal of the second capacitor and a second input terminal of the comparator circuit, and
• a second terminal of the second capacitor is coupled to the ground signal source.

A wideband jammer detector including:

• a wideband amplifier circuit,
• a peak detection circuit,
• a comparator circuit, and
• a digital jammer detection circuit,
• where a received signal is coupled to an input terminal of the wideband amplifier circuit,
• an output terminal of the wideband amplifier circuit is coupled to an input terminal of the peak detection circuit,
• an output terminal of the peak detection circuit is coupled to a first input terminal of the comparator circuit,
• a threshold signal is coupled to a second input terminal of the comparator circuit, and
• an output of the comparator circuit is coupled to an input terminal of the digital jammer detection circuit.