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US 2010/0245144 A1Published application
Sigma-delta modulator including truncation and applications thereof
AssigneeACCO Semiconductor, Inc.
InventorsMichel Robbe, Stephan Doucet
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Abstract
A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.
Claims26
A sigma-delta modulator circuit comprising:
- a first modulation stage including at least a first combiner and a first integrator, the first combiner configured to combine an input signal and a first feedback signal, the first integrator configured to integrate an output of the first combiner and to produce a first multi-bit output;
- a first truncation stage configured to receive the first multi-bit output and to truncate a least significant bit from the first multi-bit output;
- a second modulation stage including at least a second combiner and a second integrator, the second combiner configured to combine the truncated output of the first modulation stage and a second feedback signal, the second integrator being configured to integrate an output of the second combiner to produce a second multi-bit output;
- and
- a feedback generator configured to generate the first feedback signal and the second feedback signal.
2 more elements
A power amplifier comprising:
- a first sigma-delta modulator stage configured to receive an input signal and to produce a multi-bit output;
- a second sigma-delta modulator stage configured to receive an input signal generated using the first sigma-delta modulator stage;
- a first truncation stage disposed between the first sigma-delta modulator stage and the second sigma-delta modulator stage, configured to receive the multi-bit output and configured to truncate at least one of the least significant bits of the multi-bit output prior to providing the truncated multi-bit output to the second sigma-delta modulator;
- and
- a feedback generator configured to provide a gain to a feedback loop between an output of a quantizer and the first sigma-delta modulator stage.
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A method comprising:
- receiving a signal;
- combining the received signal with a first feedback signal to produce a first combined signal;
- integrating the first combined signal to produce a first multi-bit output;
- truncating the first multi-bit output;
- combining the truncated first multi-bit output with a second feedback signal to produce a second combined signal;
- integrating the second combined signal to produce a second multi-bit output;
- quantizing the second multi-bit output or an output generated using the second multi-bit output to produce a quantized signal;
- and
- using the quantized signal to produce the first feedback signal and the second feedback signal.
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Dependencies are inferred from the claim text.