US 2010/0244960 A1Published application

Differential amplifier circuit

AssigneeElpida Memory, Inc.

InventorsSeisuke TAKITANI, Kanji OISHI

Life of this patent

Estimating the term…

Loading patent…

Abstract

A differential amplifier circuit includes a plurality of differential-pair transistors, a plurality of current addition transistors, a latch, and a control transistor. The differential-pair transistors have gate electrodes that receive differential input signals respectively. Different potentials of the differential input signals represent a piece of information. The current addition transistors are connected in parallel to the differential-pair transistors, respectively. The latch has differential outputs corresponding to the differential input signals respectively and related to the amplified data. The control transistor receives an activation initiation signal. The current addition transistors are transitioned into electrically conductive state either in a period of time from initiation of amplification operation of the differential amplifier circuit by transitioning the control transistor into an electrically conductive state to increasing a differential voltage to cause inversion of one of the differential outputs of the latch, or at the same time when the amplification operation is initiated.

Claims20

Dependent claims

A differential amplifier circuit comprising:

a plurality of differential-pair transistors having gate electrodes that receive differential input signals respectively, different potentials of the differential input signals representing a piece of information;
a plurality of current addition transistors that are connected in parallel to the plurality of differential-pair transistors, respectively;
a latch connected to the plurality of differential-pair transistors, the latch being connected to the plurality of current addition transistors, the latch holding amplified data which have been generated by amplifying the plurality of differential input signals, the latch having a plurality of differential outputs, the plurality of differential outputs being related to the amplified data, the plurality of differential outputs corresponding to the differential input signals respectively;
and
a control transistor connected to the plurality of differential-pair transistors, the control transistor connected to the plurality of current addition transistors, the control transistor receiving an activation initiation signal,
wherein the plurality of current addition transistors are transitioned into electrically conductive state either in a period of time from initiation of amplification operation of the differential amplifier circuit by transitioning the control transistor into an electrically conductive state to increasing a differential voltage to cause inversion of one of the plurality of differential outputs of the latch, or at the same time when the amplification operation is initiated.

3 more elements

A differential amplifier circuit comprising:

a differential input circuit;
and a latch,
the differential input circuit comprising:
first and second transistors having gate electrodes that receive differential input signals respectively, different potentials of the differential input signals representing a piece of information;
a control transistor connected in series to the first differential-pair transistor, the control transistor being connected in series to the second differential-pair transistor, the control transistor receiving an activation initiation signal;
and
third and fourth transistors being connected in parallel to the first and second transistors,
the latch comprising first and second inverters having gates and outputs which are cross-coupled to each other,
the first and second inverters having a plurality of differential outputs having a differential voltage greater than a differential voltage of the plurality of differential input signals, related to the plurality of differential input signals, the first and second inverters outputting the plurality of differential outputs after operations of the first and second inverters,
the first and second inverters having sources which are connected in series to a plurality of outputs of the differential input circuit, the plurality of outputs of the differential input circuit corresponding to the plurality of differential input signals,
wherein the third and fourth transistors are transitioned into electrically conductive state either in a period of time from initiation of amplification operation of the first and second transistors by transitioning the control transistor into an electrically conductive state to increasing a differential voltage to cause inversion of one of the plurality of differential outputs of the latch, or at the same time when the amplification operation is initiated.

8 more elements

Dependencies are inferred from the claim text.