Compensation Techniques for Reducing Power Consumption in Digital Circuitry
AssigneeAgere Systems Inc.
InventorsJoseph Anidjar, Mohammad S. Mobin, Gregory W. Sheets, Vladimir Sindalovsky, Lane A. Smith
Life of this patent
Estimating the term…
Loading patent…
AssigneeAgere Systems Inc.
InventorsJoseph Anidjar, Mohammad S. Mobin, Gregory W. Sheets, Vladimir Sindalovsky, Lane A. Smith
Estimating the term…
A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
A compensation circuit for reducing power consumption in at least one digital circuit connected to the compensation circuit over variations in at least one of process and temperature conditions to which the digital circuit may be subjected, the compensation circuit comprising:
A method for compensating at least one digital circuit over variations in at least one of process and temperature to which the digital circuit may be subjected, the method comprising the steps of:
A voltage supply compensation system, comprising:
Dependencies are inferred from the claim text.