Semiconductor device
AssigneeRenesas Technology Corp.
InventorsMasahide Kiritani, Noriko Sonoda
Life of this patent
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Abstract
A level shifter circuit of the present invention includes a level shifter for converting a low-voltage signal to a high-voltage signal, and is provided with a unit that sets a voltage condition of an input signal to a transistor for input of the level shifter, when a high-voltage power supply is inputted to the level shifter circuit of the present invention before a low-voltage power supply.
Claims3
1-11. (canceled)
A semiconductor device to which a first power supply potential and a second power supply potential higher than said first power supply potential are supplied, the semiconductor device comprising:
- an internal circuit operated by being supplied with said first power supply potential to output a first internal signal;
- an inverter circuit operated by being supplied with said first power supply potential and having a P-channel MOS transistor and an N-channel MOS transistor within which a parasitic diode is formed to output a second internal signal obtained by inverting said first internal signal;
- a level shifter circuit operated by being supplied with said second power supply potential and having a level shifter for outputting a level shift signal depending on said first and second internal signals, which are complementary to each other, inputted to first and second input terminals, respectively;
- a current generating circuit for supplying a current to a current path to a power supply node for supplying said first power supply potential to said inverter circuit through said parasitic diode, when said second power supply is inputted before said first power supply;
- and
- a bias circuit connected between said current generating circuit and said inverter circuit.
A semiconductor device to which a first power supply potential and a second power supply potential higher than said first power supply potential are supplied, the semiconductor device comprising:
- an internal circuit operated by being supplied with said first power supply potential to output a first internal signal;
- an inverter circuit operated by being supplied with said first power supply potential and having a P-channel MOS transistor and an N-channel MOS transistor within which a parasitic diode is formed to output a second internal signal obtained by inverting said first internal signal;
- a plurality of level shifter circuits operated by being supplied with said second power supply potential and each having a level shifter for outputting a level shift signal depending on said first and second internal signals, which are complementary to each other, inputted to first and second input terminals, respectively;
- a current generating circuit for supplying a current to a current path to a power supply node for supplying said first power supply potential to said inverter circuit through said parasitic diode, when said second power supply is inputted before said first power supply;
- and
- a plurality of bias circuits arranged to correspond to said plurality of level shifter circuits and connected between said current generating circuit and said inverter circuit.
Dependencies are inferred from the claim text.