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US 2010/0244920 A1Published application
Delay circuit
AssigneeHynix Semiconductor Inc.
InventorsSeung-Joon Ahn, Jong-Chern Lee
Life of this patent
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Abstract
A delay circuit includes first and second selective delay stages each including a number of unit delay cells to delay signals applied thereto; and a delay control unit configured to control selectively applying an input signal to the first selective delay stage or the second selective delay stage in response to a code combination of first and second selection signals and produce an output signal.
Claims10
A delay circuit, comprising:
- first and second selective delay stages each including a number of unit delay cells to delay signals applied thereto;
- and
- a delay control unit configured to control selectively applying an input signal to the first selective delay stage or the second selective delay stage in response to a code combination of first and second selection signals and produce an output signal.
A delay circuit, comprising:
- a plurality of selective delay stages each including a number of unit delay cells to delay signals applied thereto;
- and
- a plurality of selection units connected in series and each receiving a selection signal allocated thereto and having a respective one of the plurality of selective delay stages assigned thereto, the selection units being each configured to be responsive to the respective selection signal to select as to whether to pass an input signal of the selection unit through the selective respective delay stage or bypass the selective respective delay stage in producing an output signal of the selection unit,
- wherein a total number of the selection units equals the total number of bits of the selection signals and the total number of unit delay cells in the respective selective delay stage of each selection unit is greater by one compared to that of the immediately preceding selection unit in the series and the total number of unit delay cells for the first selection unit in the series is one.
1 more element
A delay circuit, comprising:
- first and second selective delay stages configured to each delay an input signal applied thereto by a certain delay value;
- a first selection unit configured to be responsive to a first selection signal to select as to whether to pass an input signal of the first selection unit through the first selective delay stage or bypass the first selective delay stage in producing an output signal of the first selection unit;
- and
- a second selection unit configured to be responsive to a second selection signal to select as to whether to pass the output signal of the first selection unit through the second selective delay stage or bypass the second selective delay stage in producing an output signal of the second selection unit.
1 more element
Dependencies are inferred from the claim text.