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US 2010/0244915 A1Published application
Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSang-Hyuk Kwon, Byung Hoon Jeong, Jae Woong Lee
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Abstract
In an example embodiment, the semiconductor device includes a clock signal generation circuit. The clock signal generation circuit is configured to generate at least one control clock signal in response to an external clock signal and a read command signal. The clock signal generation circuit includes a plurality of delay circuits, and the clock signal generation circuit is configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.
Claims15
A semiconductor device, comprising:
- a signal generation circuit configured to generate an internal read command signal by delaying a read command signal and configured to generate a first clock signal by dividing an external clock signal;
- a determination unit configured to generate a control signal and an internal clock signal based on a phase of the first clock signal and a phase of a control clock signal, the internal clock signal having an identical phase or an opposite phase to the first clock signal;
- a latency control clock signal generation unit configured to generate a first latency control clock signal by delaying the internal clock signal, generate the control clock signal by delaying a second clock signal divided from the external clock signal by using a plurality of delay circuits, and generate a plurality of second latency control clock signals having different phases respectively from the second clock signal;
- and
- wherein the plurality of delay circuits are enabled or disabled in response to the control signal.
2 more elements
A semiconductor device comprising:
- a latency signal generation circuit configured to generate a latency signal in response to an external clock signal and a read command signal;
- and
- an output buffer configured to buffer received data in response to the latency signal, wherein the latency signal generation circuit includes,
- a signal generation circuit configured to generate an internal read command signal by delaying the read command signal and configured to generate a first clock signal by dividing the external clock signal;
- a determination unit configured to generate a control signal and an internal clock signal based on a phase of the first clock signal and a phase of a control clock signal, the internal clock signal having an identical phase or an opposite phase to a phase of the first clock signal;
- a latency control clock signal generation unit configured to generate a first latency control clock signal by delaying the internal clock signal, generate the control clock signal by delaying a second clock signal divided from the external clock signal by using a plurality of delay circuits, and generate a plurality of second latency control clock signals having different phases respectively from the second clock signal;
- and
- a latency generation unit for configured to adjust latency of the internal read command signal by using the first latency control clock signal and the plurality of second latency control clock signals,
- wherein the plurality of delay circuits are enabled or disabled in response to the control signal.
6 more elements
A semiconductor device, comprising:
- a clock signal generation circuit configured to generate at least one control clock signal in response to an external clock signal and a read command signal, the clock signal generation circuit including a plurality of delay circuits, and the clock signal generation circuit configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.
Dependencies are inferred from the claim text.