Power Up Biasing in a System Having Multiple Input Biasing Modes
AssigneeTexas Instruments Incorporated
InventorGary L. Swoboda
Life of this patent
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Abstract
This invention is an input bias control for a module input. A clock detect circuit generates a signal indicating whether an external clock signal is detected. An operational state detect circuit receives this signal and is responsive to an operational state of the module. The operational state detect circuit enables one of a pull-up and pull-down transistor corresponding said operational state of the module. The operational state detect circuit may the input buffer a predetermined time following external clock signal detection, which might be a following transition in the external clock signal. The operational state detect circuit enables the pull-up or pull-down transistor a predetermined time following enabling said input buffer.
Claims4
An input bias control for a module input comprising:
- an input buffer receiving an external input signal via an input terminal;
- a clock detect circuit receiving an external clock signal and generating a signal indicating whether the external clock signal is detected;
- a pull-up transistor having a source-drain path connected between a positive supply voltage and said input terminal and a gate;
- a pull-down transistor having a source-drain path connected between ground and said input terminal and a gate;
- and
- an operational state detect circuit receiving said signal indicating whether the external clock signal is detected and responsive to an operational state of the module, said operational state detect circuit connected to said gate of said pull-up transistor and said gate of said pull-down transistor, said operational state detect circuit enabling one of said pull-up and pull-down transistors corresponding said operational state of the module.
Dependencies are inferred from the claim text.