Tuning High-Side and Low-Side CMOS Data-Paths in CML-to-CMOS Signal Converter

A disk drive system, comprising:

• a differential digital logic signal to complementary metal oxide semiconductor (CMOS) signal conversion circuit, the conversion circuit comprising:
• first circuitry configured for generating a first pair of CMOS signals in response to the differential digital logic signal, the first pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity;
• second circuitry configured for adjusting, with respect to the first pair of CMOS signals, a transition time of one of the first CMOS signal and the second CMOS signal relative to a transition time of another of the first CMOS signal and the second CMOS signal;
• third circuitry configured for generating a second pair of CMOS signals in response to the differential digital logic signal, the second pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity;
• and
• fourth circuitry configured for adjusting, with respect to the second pair of CMOS signals, a transition time of one of the first CMOS signal and the second CMOS signal relative to a transition time of another of the first CMOS signal and the second CMOS signal;
• and
• a write driver configured for controlling a write head that writes data to at least one disk, the write driver being responsive to the first pair of CMOS signals and the second pair of CMOS signals.