Variable sized soft memory macros in structured cell arrays, and related methods
AssigneeAltera Corporation
InventorDavid Lewis
Life of this patent
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Abstract
The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely.
Claims12
Hybrid logic element circuitry comprising:
- first and second multiplexers, each of which has first and second selectable inputs and a selection control input for controlling which of the selectable inputs is connected to an output of the multiplexer;
- first and second inverters;
- and
- a two-input NAND gate;
- the hybrid logic element circuitry being mask-programmable to provide a memory cell by mask-programming the NAND gate to operate as a third inverter, by mask-programmably connecting two of the first through third inverters in a closed loop series that includes the first selectable input and the output of the first multiplexer, and by mask-programmably connecting a point in the closed loop series to the second multiplexer via a third of the first through third inverters.
Hybrid logic element circuitry comprising:
- first and second multiplexers, each of which has first and second selectable inputs and a selection control input for controlling which of the selectable inputs is connected to an output of the multiplexer;
- and
- first, second, and third circuit elements, each of which is selected from the group consisting of an inverter and a logical function, and each providing signal buffering;
- the hybrid logic element circuitry being mask-programmable to provide a memory cell by mask-programmably connecting two of the first through third circuit elements in a closed loop series that includes the first selectable input and the output of the first multiplexer, and by mask-programmably connecting a point in the closed loop series to the second multiplexer via a third of the first through third circuit elements.
Dependencies are inferred from the claim text.