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US 2010/0244892 A1Published application
Rom implementation for rom based logic design
AssigneeToshiba America Research, Inc.
InventorBipul C. Paul
Life of this patent
Estimating the term…
Abstract
A logic device implementing configurations for ROM based logic uses arrays of memory cells to provide outputs based on inputs received at the logic device. The logic device stores values in the memory cells that are accessed when an input is received. The memory cells are transistors that provide values of ‘1’ or ‘0.’ Various configurations reduce the number of transistors while implementing the memory block by utilizing a single bitline or a dynamic precharge implementation.
Claims18
A logic device comprising:
- an array of read-only memory (ROM) cells comprising transistors, wherein each single transistor ROM cell stores a value that is read from the cell to provide an output in response to an input pertaining to a logic design;
- a plurality of wordlines coupled to a plurality of bitlines through the single transistor ROM cells;
- and
- a transmission gate or pass transistor to select the value of the single transistor ROM cell read due to the input and provided to the output.
1 more element
A logic device comprising:
- an array of read-only memory (ROM) cells comprising transistors, wherein each cell stores a value that is read from the cell to provide an output in response to an input pertaining to a logic design;
- a plurality of wordlines coupled to the array of ROM cells;
- the cells storing a value of ‘1’ are configured in parallel and coupled to a first column select transistor;
- the cells storing a value of ‘0’ are configured in parallel and coupled to a second column select transistor,
- wherein the output is the value of ‘1’ or ‘0’ based on a cell when a bitline is selected at the first column select transistor and the second column select transistor.
2 more elements
A logic device comprising:
- a plurality of read-only memory (ROM) cells comprising transistors, wherein each cell stores a value that is read from the cell to provide an output in response to an input pertaining to a logic design, and the plurality of cells are accessible by at least one wordline and at least one bitline;
- the output is precharged to a first value;
- the plurality of cells store a second value;
- and
- a clock signal used to precharge the output and evaluate the plurality of cells.
2 more elements
Dependencies are inferred from the claim text.