Method and Apparatus for Diagnosing an Integrated Circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKin Lam Tong, Wei-Pin Changchein, Chin-Chou Liu
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Abstract
System and method for diagnosing failures within an integrated circuit is provided. In an embodiment, the apparatus includes a diagnostic cell coupled in series with a buffer chain. The diagnostic cell includes a plurality of logic operators that when activated invert a signal received from the buffer chain. The inversion of the signal from the buffer chain allows the diagnostic cell to determine the location of a failure within an integrated circuit previously determined by a scan chain design for test methodology to contain a failure.
Claims20
An apparatus for diagnosing an integrated circuit comprising:
- a plurality of flip-flops, configured for scan chain design for test;
- a buffer chain having a plurality of buffers, the buffer chain communicatively coupled to a first flip-flop of the plurality of flip flops;
- a first diagnosis cell, communicatively coupled in series with the buffer chain, configured to receive a buffer chain output signal from a first intermediate buffer in the buffer chain, a first input signal, and a second input signal, and produce a diagnostic signal indicating the operational status of the integrated circuit;
- and
- a second intermediate buffer configured to receive the diagnostic signal and transmit the diagnostic signal to a second flip-flop of the plurality of flip-flops.
An apparatus for diagnosing an integrated circuit comprising:
- a diagnostic cell comprising a first logic operator coupled to a second logic operator, the first logic operator configured to receive a first input signal and a second input signal, and in response, produce a first logic operator output signal;
- and
- the second logic operator configured to receive a third input signal and the first logic operator output signal, and in response produce a diagnostic signal indicating an operational status at a given location in the integrated circuit.
A method for diagnosing an integrated circuit comprising:
- testing the integrated circuit using a scan chain test pattern;
- if the testing indicates that the integrated circuit does not perform as designed, enabling one or more diagnostic cells at one or more locations within the integrated circuit;
- re-testing the integrated circuit using the scan chain test pattern, the one or more diagnostic cells selectively inverting an operational signal within the integrated circuit;
- and
- identifying an operational status at a first location of the one or more locations based on the re-test of the integrated circuit.
Dependencies are inferred from the claim text.