System for testing connections between chips

A system comprising:

• a first chip;
• a second chip;
• a connection configured to connect a first pin of the first chip to a first pin of the second chip, and to transmit an initial signal from the first chip to the second chip,
• wherein the connection comprises a return path configured to connect the first pin of the first chip to a second pin of the first chip, and to return the initial signal to the first chip, and
• wherein the first chip comprises circuitry configured to compare the returned signal with the initial signal.

A system comprising:

• a first chip comprising a first control logic and a first pad structure;
• a second chip comprising a second control logic and a second pad structure;
• and
• a plurality of interconnections coupling the first and second pad structures;
• wherein the first control logic is configured to cause the first pad structure to transmit a test signal to the second pad structure via the plurality of interconnections,
• wherein the second control logic is configured to cause the second pad structure to return the test signal to the first pad structure via the plurality of interconnections, and
• wherein the first pad structure is configured to compare the test signal with the test signal returned from the second pad structure.

A system for testing a plurality of interconnections between a plurality of chips, the system comprising:

• a first control logic implemented in a first chip of the plurality of chips;
• a second control logic implemented in a second chip of the plurality of chips;
• and
• a control unit coupled to the first control logic and to the second control logic, wherein the control unit is configured to transmit control signals to the first control logic and to the second control logic to cause:
• the first control logic to transmit signals to and receive signals from the second control logic over the plurality of interconnections,
• the second control logic to transmit signals to and receive signals from the first control logic over the plurality of interconnections,
• the first control logic to compare corresponding pairs of sent and received signals to determine if signals are transmitted correctly over a respective interconnection of the plurality of interconnections between the first and second chip, and
• the second control logic to compare corresponding pairs of sent and received signals to determine if signals are transmitted correctly over a further respective interconnection of the plurality of interconnections between the first and second chip.