Method and circuit for low power voltage reference and bias current generator
AssigneeAnalog Devices, Inc.
InventorStefan MARINCA
Life of this patent
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Abstract
A system and method are provided for a PTAT cell with no resistors which can operate at low power, has less sensitivity to process variation, occupies less silicon area, and has low noise. Further, a system and method are provided to scale up the reference voltage and current through a cascade of unit cells. Still further, a system and method are provided for PTAT component to be fine-tuned, advantageously providing less process variability and less temperature sensitivity.
Claims46
A proportional to absolute temperature (PTAT) voltage circuit configured to provide a voltage reference at an output thereof, the circuit comprising:
- a first set of circuit elements, the first set of circuit elements arranged to provide a complimentary to absolute temperature (CTAT) voltage or current;
- and
- a second set of circuit elements, the second set of circuit elements arranged to provide a proportional to absolute temperature (PTAT) voltage or current, wherein
- the second set of circuit elements includes at least one bipolar transistor and an active element being resistorless, the active element having a resistance, and
- the first set of circuit elements includes at least one bipolar transistor operated at n times a current density of the at least one bipolar transistor of the second set of circuit elements.
A proportional to absolute temperature (PTAT) voltage circuit configured to provide a voltage reference at an output thereof, the circuit comprising a cascade of unit cells, each unit cell comprising:
- a first set of circuit elements, the first set of circuit elements arranged to provide a complimentary to absolute temperature (CTAT) voltage or current;
- and
- a second set of circuit elements, the second set of circuit elements arranged to provide a PTAT voltage or current, wherein
- the second set of circuit elements includes at least one bipolar transistor and an active element being resistorless, the active element having a resistance, and
- the first set of circuit elements includes at least one bipolar transistor operated at n times a current density of the at least one bipolar transistor of the second set of circuit elements, and the voltage reference is substantially equal to a voltage reference of each unit cell multiplied by the number of unit cells.
A method of providing a PTAT voltage circuit configured to provide a voltage reference at an output thereof, the method comprising:
- providing a first set of circuit elements, the first set of circuit elements arranged to provide a complimentary to absolute temperature (CTAT) voltage or current;
- and
- providing a second set of circuit elements, the second set of circuit elements arranged to provide a PTAT voltage or current, wherein
- the second set of circuit elements includes at least one bipolar transistor and an active element being resistorless, the active element having a resistance, and
- the first set of circuit elements includes at least one bipolar transistor operated at n times a current density of the at least one bipolar transistor of the second set of circuit elements.
The method according to claim 33, wherein the active element of the second set of circuit element limits a collector voltage of the at least one bipolar transistor of the second set of circuit elements, thereby reducing an Early Voltage (VA) of the at least one bipolar transistor of the second set of circuit elements.
The method according to claim 33, wherein the first set of circuit elements include at least one MOSFET which supplies a base current of the at least one bipolar transistor of the first set of circuit elements and a base current of the at least one bipolar transistor of the second set of circuit elements.
The method according to claim 35, wherein the at least one MOSFET of the first set of circuit elements reduces an Early Voltage (VA) of the at least one bipolar transistor of the first set of circuit elements.
The method according to claim 33, wherein collector bias currents of the first set of circuit elements and the second set of circuit elements are generated from a resistorless bias generator.
The method according to claim 33, wherein the active element that is resistorless from the second set of circuit elements is a MOSFET.
The method according to claim 38, wherein the output is not sensitive to offset voltages and noise introduced by the at least one MOSFET from the first set of circuit elements and the MOSFET from the second set of circuit elements.
The method according to claim 33, further comprising a third set of circuit elements, the third set of circuit elements including a series of resistances, each of the series of resistances having a respective output that can be tapped, arranged to divide the CTAT voltage to generate a temperature independent voltage reference at the output.
The method according to claim 40, wherein the series of resistances comprise NMOSs operated in the linear or triode region.
The method according to claim 40, wherein the number of series resistances depends on a resolution of a desired CTAT division.
The method according to claim 42, wherein the voltage reference is tapped at an output of a resistance of the series resistances that is most temperature independent.
The method according to claim 40, further comprising a fourth set of circuit elements arranged to provide an independent current output that is not sensitive to temperature variations.
The method according to claim 44, wherein the fourth set of circuit elements include an amplifier and a resistance coupled to an inverting terminal of the amplifier.
The method according to claim 45, wherein a non-inverting terminal of the amplifier is configured to have a specific temperature variation to compensate for a temperature coefficient of the resistance coupled to the inverting terminal of the amplifier.
The method according to claim 44, wherein one of the outputs of the series resistances is tapped as the input for the non-inverting terminal of the amplifier.
A method of providing a proportional to absolute temperature (PTAT) voltage circuit configured to provide a voltage reference at an output thereof, the circuit comprising a cascade of unit cells, the method comprising:
- providing for each unit cell a first set of circuit elements, the first set of circuit elements arranged to provide a complimentary to absolute temperature (CTAT) voltage or current,
- providing for each unit cell a second set of circuit elements, the second set of circuit elements arranged to provide a PTAT voltage or current, wherein, for each unit cell,
- the second set of circuit elements includes at least one bipolar transistor and an active element that is resistorless and has resistance, and
- the first set of circuit elements includes at least one bipolar transistor operated at n times a current density of the at least one bipolar transistor of the second set of circuit elements, and the voltage reference is substantially equal to a voltage reference of each unit cell multiplied by the number of unit cells.
The method according to claim 49, wherein in each unit cell the active element of the second set of circuit element limits a collector voltage of the at least one bipolar transistor of the second set of circuit elements, thereby reducing an Early Voltage (VA) of the at least one bipolar transistor of the second set of circuit elements.
The method according to claim 49, further comprising a third set of circuit elements, the third set of circuit elements including a series of resistances, each of the series of resistances having a respective output that can be tapped, arranged to divide the CTAT voltage to generate a temperature independent voltage reference at the output.
The method according to claim 49, wherein in each unit cell the PTAT voltage is increased by including at least one stack transistor in the first set of circuit elements and at least one stack transistor in the second set of current elements, wherein the at least one stack transistor of the first set of circuit elements is operated at n times a current density of the at least one stack transistor of the second set of circuit elements.
The method according to claim 71, wherein the selective shorting is performed through digital trimming.
The method according to claim 72, wherein the digital trimming is through a coarse string and a fine string.
Dependencies are inferred from the claim text.