Stacked multichip package

A stacked multichip package, comprising:

• a first chip having a first active surface and a first rear surface;
• a first chip carrier having a first opening, the first chip carrier being attached to the first active surface;
• a plurality of first conductive leads passing through the first opening and configured to electrically couple the first active surface to the first chip carrier;
• a second chip having a second active surface and a second rear surface;
• an adhesive layer surrounding the plurality of first conductive leads and configured to bond the first chip carrier to the second rear surface;
• a second chip carrier having a second opening, the second chip carrier being attached to the second active surface;
• a plurality of second conductive leads passing through the second opening and configured to electrically coupled the second active surface to the second chip carrier;
• and
• a plurality of third conductive leads for electrically coupling the first chip carrier to the second chip carrier.