Semiconductor package fabrication process and semiconductor package

A semiconductor package comprising:

• a substrate having a front face and a rear face and including a sheet provided with electrical connection pads including front pads and rear pads that are selectively connected via an electrical connection network passing through the substrate;
• at least one integrated-circuit chip having a face which is fastened to the front face of the substrate using a layer of a dielectric sealant, the chip including electrical connection pads placed selectively above the front pads of the substrate, wherein the pads of the chip and the front pads of the substrate are electrically connected via particles of an electrically conductive material contained in the sealant;
• and
• an encapsulant for the integrated-circuit chip provided in front of the front face of the substrate.

A process for fabricating semiconductor packages, comprising:

• mounting a peripheral edge of a substrate on a rigid annular frame;
• depositing a layer of a dielectric sealant on a front face of the substrate, the sealant containing particles made of an electrically conductive material;
• attaching a plurality of integrated-circuit chips to the front face of the substrate using the deposited sealant, wherein attaching comprises flattening the sealant so as to promote the making of electrical connections between each chip and the substrate using the contained particles;
• forming an encapsulating block of material over the chips and the front face of the substrate so as to produce a mounted assembly;
• and
• dicing the mounted assembly between integrated-circuit chips in order to obtain a plurality of semiconductor packages each comprising a portion of the substrate and at least one integrated-circuit chip.