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US 2010/0244198 A1Published application
Cmos sige channel pfet and si channel nfet devices with minimal sti recess
AssigneeInternational Business Machines Corporation
InventorsDaniel J. Jaeger, Michael ` V. Aquilino, Christopher V. Baiocco
Life of this patent
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Abstract
Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.
Claims25
A method of forming a device, comprising:
- providing a wafer having a pad oxide layer, the wafer including a silicon substrate having nFET regions and pFET regions;
- removing the pad oxide layer to expose a silicon channel above the nFET regions and the pFET regions;
- growing an epitaxial layer on the silicon channel;
- applying a positive photoresist layer on the epitaxial layer above the pFET regions;
- removing the epitaxial layer above the nFET regions;
- and
- removing the positive photoresist layer.
4 more elements
A method of forming a device, comprising:
- providing a wafer having a pad oxide layer, the wafer including a silicon substrate and having nFET regions and pFET regions;
- removing the pad oxide layer to expose a silicon channel above the nFET regions and the pFET regions;
- performing a wet oxide etch preclean on the silicon channel;
- growing a silicon germanium (SiGe) epitaxial layer on the silicon channel;
- depositing a hardmask layer on the silicon germanium (SiGe) epitaxial layer;
- applying a positive photoresist layer on the hardmask layer above the pFET regions;
- removing the hardmask layer above the nFET regions;
- removing the positive photoresist layer;
- removing the silicon germanium (SiGe) epitaxial layer above the nFET regions;
- and
- removing the hardmask layer above the pFET regions.
8 more elements
A method of forming a device, comprising:
- providing a wafer having a pad oxide layer, the wafer including a silicon substrate and having nFET regions and pFET regions;
- removing the pad oxide layer to expose a silicon channel above the nFET regions and the pFET regions;
- performing a wet oxide etch preclean on the silicon channel;
- growing a silicon germanium (SiGe) epitaxial layer on the silicon channel;
- depositing a first hardmask layer on the silicon germanium (SiGe) epitaxial layer;
- depositing a second hardmask layer on the first hardmask layer;
- applying a positive photoresist layer on the second hardmask layer above the pFET regions;
- removing the second hardmask layer above the nFET regions;
- removing the positive photoresist layer;
- removing the first hardmask layer above the nFET regions;
- removing the silicon germanium (SiGe) epitaxial layer above the nFET regions;
- removing the second hardmask layer above the pFET regions;
- and
- removing the first hardmask layer above the pFET regions.
11 more elements
A device, comprising:
- a wafer, the wafer including a silicon substrate having nFET regions and pFET regions;
- a silicon channel above the nFET regions;
- and
- an epitaxial layer above the pFET regions.
1 more element
Dependencies are inferred from the claim text.