Maintaining integrity of a high-k gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy

A method, comprising:

• forming a first offset spacer element at least on a portion of sidewalls of a first gate stack, said first gate stack being formed above a first semiconductor region;
• forming a deposition mask above a second semiconductor region having formed thereabove a second gate stack, said first and second gate stacks comprising a high-k dielectric gate insulation layer, a metal-containing electrode material formed on said high-k dielectric gate insulation layer and a cap layer;
• forming a semiconductor alloy in said first semiconductor region by using said first offset spacer element as a mask;
• forming a second offset spacer element on at least a portion of said second gate stack;
• and
• removing said cap layers of said first and second gate stacks while maintaining at least a portion of said first and second offset spacer elements.

A transistor device, comprising:

• a gate electrode structure comprising a metal-containing electrode material formed on a gate insulation layer comprising a high-k dielectric material;
• an active region comprising a channel region, drain and source regions and a strain-inducing semiconductor alloy;
• and
• a spacer structure formed on sidewalls of said gate electrode structure, said spacer structure comprising a protection spacer that is in direct contact with a sidewall face of said gate insulation layer, said protection spacer having a width that is substantially equal to a lateral offset of said strain-inducing semiconductor alloy from said sidewall face.