Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor

A structure comprising a principal field-effect transistor (“FET”) provided along an upper surface of a semiconductor body, the FET comprising:

• a first well region situated in the semiconductor body and doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, the dopant of the first conductivity type having a concentration that locally reaches a subsurface concentration maximum in the first well region at a first subsurface location extending generally laterally below the semiconductor body's upper surface;
• a source and a drain of a second conductivity type opposite to the first conductivity type situated in the semiconductor body and extending to its upper surface, a channel zone of the semiconductor body laterally separating the source and drain, being of the first conductivity type, and comprising part of the first well region, the source situated above the location of the subsurface concentration maximum of the first well region, the drain comprising a second well region doped with semiconductor dopant of the second conductivity type, the dopant of the second conductivity type having a concentration that locally reaches a subsurface concentration maximum in the second well region at a second subsurface location extending generally laterally below the semiconductor body's upper surface;
• a well-separating portion of the semiconductor body extending between the well regions and being more lightly doped than each well region 'such that the locations of the subsurface concentration maxima of the well regions are spaced laterally apart from each other;
• a gate dielectric layer the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone.

A structure comprising a principal field-effect transistor (“FET”) provided along an upper surface of a semiconductor body, the FET comprising:

• a first well region situated in the semiconductor body, extending to its upper surface, and being of a first conductivity type;
• first and second source/drain (“S/D”) zones of a second conductivity type opposite to the first conductivity type situated in the semiconductor body and extending to its upper surface, a channel zone of the semiconductor body laterally separating the S/D zones, being of the first conductivity type, and comprising part of the first well region, the first S/D zone adjoining the first well region, the second S/D zone comprising a second well region of the second conductivity type spaced laterally apart from the first well region;
• a well-separating portion of the semiconductor body extending between the well regions and being more lightly doped than each well region;
• a gate dielectric layer the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone, the FET having an electric field whose peak magnitude in the semiconductor body occurs significantly below its upper surface when the FET is non-conductive with the S/D zones biased for enabling charge carriers to flow from the first S/D zone to the second S/D zone if the FET were conductive.

A structure comprising a principal field-effect transistor (“FET”) provided along an upper surface of a semiconductor body, the FET comprising:

• a first well region situated in the semiconductor body, extending to its upper surface, and being of a first conductivity type;
• a source and a drain of a second conductivity type opposite to the first conductivity type situated in the semiconductor body and extending to its upper surface, a channel zone of the semiconductor body laterally separating the source and drain, being of the first conductivity type, and comprising part of the first well region, the source adjoining the first well region, the drain comprising a second well region of the second conductivity type spaced laterally apart from the first well region;
• a well-separating portion of the semiconductor body extending between the well regions and being more lightly doped than each well region;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone, the FET having an electric field whose peak magnitude in the semiconductor body occurs significantly below its upper surface when the FET is non-conductive with the source and drain biased for enabling charge carriers to flow from the source to the drain if the FET were conductive.

A method comprising:

• introducing primary semiconductor dopant of a first conductivity type and first semiconductor dopant of a second conductivity type opposite to the first conductivity type into a semiconductor body to respectively define first and second well regions respectively of the first and second conductivity types such the dopants have respective concentrations which reach respective concentration maxima respectively inside the well regions at a pair of laterally extending locations spaced laterally apart from each other;
• defining a gate electrode for a principal field-effect transistor (“FET”) above, and vertically separated by a gate dielectric layer for the FET from, a portion of the semiconductor body intended to be a channel zone of the FET such that the channel zone is of the first conductivity type and comprises part of the first well region;
• and
• introducing second semiconductor dopant of the second conductivity type into the semiconductor body to define a first source/drain (“S/D”) zone of the FET such that (i) the first S/D zone is situated above the location of the subsurface concentration maximum of the first well region, (ii) a second S/D zone of the FET comprises the second well region, (iii) the channel zone laterally separates the S/D zones, and (iv) a well-separating portion of the semiconductor body separates the well regions and is more lightly doped than each well region.

A method comprising:

• introducing primary semiconductor dopant of a first conductivity type and first semiconductor dopant of a second conductivity type opposite to the first conductivity type into a semiconductor body to respectively define first and second well regions respectively of the first and second conductivity types such the dopants have respective concentrations which reach respective concentration maxima respectively inside the well regions at first and second laterally extending subsurface locations spaced laterally apart from each other;
• defining a gate electrode for a principal field-effect transistor (“FET”) above, and vertically separated by a gate dielectric layer for the FET from, a portion of the semiconductor body intended to be a channel zone of the FET such that the channel zone is of the first conductivity type and comprises part of the first well region;
• and
• introducing second semiconductor dopant of the second conductivity type into the semiconductor body to define a source of the FET such that (i) the source is situated above the location of the subsurface concentration maximum of the first well region, (ii) a drain of the FET comprises the second well region, (iii) the channel zone laterally separates the source and drain, and (iv) a well-separating portion of the semiconductor body separates the well regions and is more lightly doped than each well region.

A method as in claim 38 wherein the act of introducing the second dopant of the second conductivity type comprises:

• introducing semiconductor dopant of the second conductivity type through an opening in a first mask and into at least a segment of the semiconductor body intended for the lateral source extension using the first mask, the gate electrode, and any material along the gate electrode as a dopant-blocking shield;
• providing spacer material to at least the transverse side of the gate electrode closest to where the source is to be present;
• and
• introducing semiconductor dopant of the second conductivity type through an opening in the second mask and into a segment of the semiconductor body intended for the main source portion using the second mask, the gate electrode, and the spacer material as a dopant-blocking shield.

A method comprising:

• introducing primary semiconductor dopant of a first conductivity type and first semiconductor dopant of a second conductivity type opposite to the first conductivity type into a semiconductor body to respectively define first and second well regions respectively of the first and second conductivity types;
• defining a gate electrode for a principal field-effect transistor (“FET”) above, and vertically separated by a gate dielectric layer for the FET from, a portion of the semiconductor body intended to be a channel zone of the FET such that the channel zone is of the first conductivity type and comprises part of the first well region;
• introducing second semiconductor dopant of the second conductivity type into the semiconductor body to define a first source/drain (“S/D”) zone of the FET such that a second S/D zone of the FET comprises the second well region, the channel zone laterally separates the S/D zones, and a well-separating portion of the semiconductor body separates the well regions and is more lightly doped than each well region;
• and
• maintaining the FET in a non-conductive condition with the S/D zones biased for enabling charge carriers to flow from the first S/D zone to the second S/D zone if the FET were conductive such that the FET then has an electric field whose peak magnitude in the semiconductor body occurs significantly into the semiconductor body.

A method comprising:

• introducing primary semiconductor dopant of a first conductivity type and first semiconductor dopant of a second conductivity type opposite to the first conductivity type into a semiconductor body to respectively define first and second well regions respectively of the first and second conductivity types;
• defining a gate electrode for a principal field-effect transistor (“FET”) above, and vertically separated by a gate dielectric layer for the FET from, a portion of the semiconductor body intended to be a channel zone of the FET such that the channel zone is of the first conductivity type and comprises part of the first well region;
• introducing second semiconductor dopant of the second conductivity type into the semiconductor body to define a source of the FET such that a drain of the FET comprises the second well region, the channel zone laterally separates the source and drain, and a well-separating portion of the semiconductor body separates the well regions and is more lightly doped than each well region;
• and
• maintaining the FET in a non-conductive condition with the source and drain biased for enabling charge carriers to flow from the source to the drain if the FET were conductive such that the FET then has an electric field whose peak magnitude in the semiconductor body occurs significantly into the semiconductor body.