Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses

A structure comprising a plurality of like-polarity field-effect transistors (“FETs”) provided along an upper surface of a semiconductor body having body material of a first conductivity type, each FET comprising:

• a channel zone of the body material;
• first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body material, each S/D zone comprising a main S/D portion and a more lightly doped lateral S/D extension laterally continuous with the main S/D portion and extending laterally under the gate electrode such that the channel zone is terminated by the S/D extensions along the body's upper surface;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone, wherein (a) the S/D extensions of the S/D zones of a first of the FETs are constituted or/and configured differently than the S/D extensions of the S/D zones of a second of the FETs and (b) the S/D extension of a specified one of the S/D zones of the first FET extends less deeply below the body's upper surface than the S/D extension of a specified one of the S/D zones of the second FET.

A method of fabricating a plurality of like-polarity field-effect transistors (“FETs”) from a semiconductor body having body material of a first conductivity type, the method comprising:

• defining a gate electrode for each FET such that the gate electrode is situated above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone for that FET;
• and
• introducing composite semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to form, for each FET, a pair of source/drain (“S/D”) zones of the second conductivity type laterally separated by that FET's channel zone and forming a pair of pn junctions respectively with the S/D zones such that each S/D zone comprises a main S/D portion and a more lightly doped lateral S/D extension laterally continuous with the main S/D portion and extending laterally under the gate electrode and such that the channel zone is terminated by the S/D extensions directly below that FET's gate dielectric layer wherein the act of introducing the composite dopant of the second conductivity type includes (a) introducing first semiconductor dopant of the second conductivity type into the semiconductor body to at least partially define the S/D extension of a specified one of the S/D zones of a first of the FETs and (b) introducing second semiconductor dopant of the second conductivity type into the semiconductor body to at least partially define the S/D extension of a specified one of the S/D zones of a second of the FETs, the first dopant of the second conductivity type being introduced at a higher dosage than the second dopant of the second conductivity type so that the S/D extension of the specified S/D zone of the first FET is more heavily doped than the S/D extension of the specified S/D zone of the second FET.

A method of fabricating a plurality of like-polarity field-effect transistors (“FETs”) from a semiconductor body having body material of a first conductivity type, the method comprising:

• defining a gate electrode for each FET such that the gate electrode is situated above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone for that FET;
• and
• introducing composite semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to form, for each FET, a pair of source/drain (“S/D”) zones of the second conductivity type laterally separated by that FET's channel zone and forming a pair of pn junctions respectively with the S/D zones such that each S/D zone comprises a main S/D portion and a more lightly doped lateral S/D extension laterally continuous with the main S/D portion and extending laterally under the gate electrode and such that the channel zone is terminated by the S/D extensions directly below that FET's gate dielectric layer wherein the act of introducing the composite dopant of the second conductivity type includes (a) introducing first semiconductor dopant of the second conductivity type into the semiconductor body to at least partially define the S/D extension of a specified one of the S/D zones of a first of the FETs and (b) introducing second semiconductor dopant of the second conductivity type into the semiconductor body to at least partially define the S/D extension of a specified one of the S/D zones of a second of the FETs, the first dopant of the second conductivity type being introduced at a lower average depth into the semiconductor body than the second dopant of the second conductivity type so that the S/D extension of the specified S/D zone of the first FET extends less deeply into the semiconductor body than the S/D extension of the specified S/D zone of the second FET.