Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone

A structure comprising a field-effect transistor provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, the transistor comprising:

• a channel zone of the body material;
• a source and a drain situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body material, a pocket portion of the body material more heavily doped than laterally adjacent material of the body material extending along the source and into the channel zone substantially up to the body's upper surface so as to cause the channel zone to be asymmetric with respect to the source and drain, the dopant of the first conductivity type having a concentration which reaches a plurality of local maxima at respective locations (i) spaced apart from one another in the body material along an imaginary line extending through the body material generally perpendicular to the body's upper surface, (ii) extending generally laterally across the pocket portion, and (iii) substantially spaced apart from the drain so as to cause the pocket portion to have a net dopant concentration which reaches a like plurality of respectively corresponding local maxima at respective locations spaced apart from one another in the pocket portion;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone.

A structure comprising a field-effect transistor provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, the transistor comprising:

• a channel zone of the body material;
• first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body material, a pocket portion of the body material more heavily doped than laterally adjacent material of the body material extending along largely only the first of the S/D zones and into the channel zone substantially up to the body's upper surface so as to cause the channel zone to be asymmetric with respect to the S/D zones, the dopant of the first conductivity type having a concentration which varies by a factor of no more than 2.5 in moving from the body′ upper surface along an imaginary line extending through the pocket portion generally perpendicular to the body's upper surface to a depth of at least 50% of that of the pocket portion along the imaginary line;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone.

A structure comprising a field-effect transistor provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, the transistor comprising:

• a channel zone of the body material;
• a source and a drain situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body material, a pocket portion of the body material more heavily doped than laterally adjacent material of the body material extending along the source and into the channel zone substantially up to the body's upper surface so as to cause the channel zone to be asymmetric with respect to the source and drain, the dopant of the first conductivity type having a concentration which varies by a factor of no more than 2.5 in moving from the body′ upper surface along an imaginary line extending through the pocket portion generally perpendicular to the body's upper surface to a depth of at least 50% of that of the pocket portion along the imaginary line;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone.

A method of fabricating a semiconductor structure from a semiconductor body having body material of a first conductivity type, the method comprising:

• defining a gate electrode above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone;
• and
• subsequently introducing (i) semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to define first and second source/drain (“S/D”) zones of the second conductivity type laterally separated by the channel zone and (ii) pocket semiconductor dopant of the first conductivity type into at least the intended channel-zone portion of the body material to define a pocket portion of the body material more heavily doped than laterally adjacent material of the body material and extending largely along only the first of the S/D zones and into the channel zone so as to cause the channel zone to be asymmetric with respect to the S/D zones, the pocket dopant being so introduced at a plurality of different dopant-introduction conditions such that the pocket portion has a net dopant concentration which reaches a like plurality of respectively corresponding local maxima at respective locations spaced along an imaginary line that extends vertically through the pocket portion whereby a field-effect transistor is comprised by the S/D zones, the channel zone, the pocket portion, the gate dielectric layer, and the gate electrode.

A method of fabricating a semiconductor structure from a semiconductor body having body material of a first conductivity type, the method comprising:

• defining a gate electrode above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone ;
• and
• subsequently introducing (i) composite semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to define a source and a drain of the second conductivity type laterally separated by the channel zone and (ii) pocket semiconductor dopant of the first conductivity type into at least the intended channel-zone portion of the body material to define a pocket portion of the body material more heavily doped than laterally adjacent material of the body material and extending largely along only the source and into the channel zone so as to cause the channel zone to be asymmetric with respect to the source and drain, the pocket dopant being so introduced at a plurality of different dopant-introduction conditions such that the pocket portion has a net dopant concentration which reaches a like plurality of respectively corresponding local maxima at respective locations spaced along an imaginary line that extends vertically through the pocket portion whereby a field-effect transistor is comprised by the source, the drain, the channel zone, the pocket portion, the gate dielectric layer, and the gate electrode.

A method of fabricating a semiconductor structure from a semiconductor body having body material of a first conductivity type, the method comprising:

• defining a gate electrode above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone;
• and
• subsequently introducing (i) semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to define first and second source/drain (“S/D”) zones of the second conductivity type laterally separated by the channel zone and (ii) pocket semiconductor dopant of the first conductivity type into at least the intended channel-zone portion of the body material to define a pocket portion of the body material more heavily doped than laterally adjacent material of the body material and extending largely along only the first of the S/D zones and into the channel zone so as to cause the channel zone to be asymmetric with respect to the S/D zones, the pocket dopant being so introduced such that it has a concentration which varies by a factor of no more than 2.5 in moving largely from the gate dielectric layer along an imaginary line extending through the pocket portion generally perpendicular to the gate dielectric layer to a depth of at least 50% of that of the pocket portion along the imaginary line whereby a field-effect transistor is comprised by the S/D zones, the channel zone, the pocket portion, the gate dielectric layer, and the gate electrode.

A method of fabricating a semiconductor structure from a semiconductor body having body material of a first conductivity type, the method comprising:

• defining a gate electrode above, and vertically separated by a gate dielectric layer from, a portion of the body material intended to be a channel zone;
• and
• subsequently introducing (i) composite semiconductor dopant of a second conductivity type opposite to the first conductivity type into the semiconductor body to define a source and a drain of the second conductivity type laterally separated by the channel zone and (ii) pocket semiconductor dopant of the first conductivity type into at least the intended channel-zone portion of the body material to define a pocket portion of the body material more heavily doped than laterally adjacent material of the body material and extending largely along only the source and into the channel zone so as to cause the channel zone to be asymmetric with respect to the source and drain, the pocket dopant being so introduced such that it has a concentration which varies by a factor of no more than 2.5 in moving largely from the gate dielectric layer along an imaginary line extending through the pocket portion generally perpendicular to the gate dielectric layer to a depth of at least 50% of that of the pocket portion along the imaginary line whereby a field-effect transistor is comprised by the source, the drain, the channel zone, the pocket portion, the gate dielectric layer, and the gate electrode.