Electrical fuse and related applications
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsFu-Lung HSUEH, Tao Wen CHUNG, Po-Yao KE, Shine CHUNG
Life of this patent
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Abstract
In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.
Claims22
An electrical fuse comprising:
- a conductive layer;
- a fin region that is part of a semiconductor fin structure, is below and in contact with the conductive layer, and includes
- a first region having a first dopant conductivity;
- a second region having a second dopant conductivity;
- a junction between the first region and the second region;
- a first contact region disposed over the first region and coupled to a first side of the conductive layer;
- and
- a second contact region disposed over the second region and coupled to a second side of the conductive layer;
- wherein the first contact region and the second contact region act as terminals for the electrical fuse.
A memory cell comprising:
- a transistor having a first transistor contact region and a second transistor contact region;
- an electrical fuse having a first fuse contact region and a second fuse contact region;
- the electrical fuse being formed on top of a fin of a FinFET structure and defining a logic level of the memory cell;
- the first fuse contact region and the second fuse contact region acting as terminals of the fuse;
- a conductive line connecting the first transistor contact region and the first fuse contact region;
- the second transistor contact region being used to detect the logic level of the memory cell.
A semiconductor fuse comprising:
- a substrate;
- a first layer formed on top of the substrate;
- a first dopant region and a second dopant region that are
- separately apart from one another;
- formed in the substrate;
- and
- under and in contact with the first layer;
- a first terminal and a second terminal that are
- formed on top of the first dopant region and the dopant second region, respectively;
- in contact with the first layer;
- and
- act as terminals for the fuse;
- and
- a third region and a fourth region that are
- formed on top of the first layer;
- and
- separately apart form one another;
- a space between the third region and the fourth region forms a width of the fuse.
A memory cell comprising:
- a transistor;
- a fuse coupled to the transistor and including
- a substrate;
- a first layer formed on top of the substrate;
- a first region and a second region formed on top of the first layer;
- a space between the first region and the second region forms a width of the fuse;
- and
- a first terminal and a second terminal;
- and
- a logic level determined by impedance between the first terminal and the second terminal.
Dependencies are inferred from the claim text.