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US 2010/0244132 A1Published application
Methods for Normalizing Strain in Semiconductor Devices and Strain Normalized Semiconductor Devices
AssigneeInternational Business Machines Corporation
InventorsBruce Balch, Kerry Bernstein, John Joseph Ellis-Monaghan, Nazmul Habib
Life of this patent
Estimating the term…
Abstract
A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor.
Claims25
A method, comprising:
- forming first and second field effect transistors of an integrated circuit;
- forming a stress layer over said first and second field effect transistors, said stress layer inducing strain in channel regions of said first and second field effect transistors;
- and
- selectively thinning said stress layer over at least a portion of said second field effect transistor.
1 more element
A method, comprising:
- determining spatial relationships between design shapes of selected levels of a design of field effect transistors of an integrated circuit;
- generating an estimate of strains that would be induced in channel regions of said field effect transistors by a stress layer formed over said field effect transistors based on said spatial relationships;
- generating a stress layer photomask based on said design shapes of said selected design levels and said estimate of strains;
- and
- using said stress layer photomask, selectively thinning said stress layer over at least a portion of one of said field effect transistors.
2 more elements
A structure, comprising:
- first and second field effect transistors of an integrated circuit;
- and
- a stress layer having an integral first region having a first thickness over said first field effect transistor and an integral second region having a second thickness over said second field effect transistor, said first region of said stress layer inducing a first amount of strain in a channel region of said first field effect transistor and said second region of said stress layer inducing a second amount of strain in a channel region of said second field effect transistor;
- and
- wherein, said first thickness is greater than said second thickness.
2 more elements
Dependencies are inferred from the claim text.