Configuration and fabrication of semiconductor structure using empty and filled wells

A structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the FETs being provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, each FET comprising:

• a channel zone of a region of the body material;
• first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body-material region such that (a) each pn junction reaches a maximum depth below the body's upper surface, (b) the body-material region extends laterally under both S/D zones, and (c) the dopant of the first conductivity type is present in both S/D zones and has a concentration which locally reaches a main subsurface maximum concentration at a main subsurface maximum concentration location extending laterally below largely all of each of the channel and S/D zones, and (d) the main subsurface maximum concentration location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone wherein the concentration of the dopant of the first conductivity type (i) decreases by at least a factor of 10 in moving upward from the main subsurface maximum concentration location for each first FET along a selected vertical location for that first FET through a specified one of the S/D zones of that first FET to the body's upper surface, (ii) decreases substantially monotonically by less than a factor of 10 in moving from the main subsurface maximum concentration location for that first FET along the selected vertical location for that first FET to the pn junction for the specified S/D zone of that first FET, and (iii) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration for that second FET occurs at an additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of that second FET overlying its channel zone and at least part of each of its S/D zones.

A structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the FETs being provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, each FET comprising:

• a channel zone of a region of the body material;
• first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body-material region such that (a) each pn junction reaches a maximum depth below the body's upper surface, (b) the body-material region extends laterally under both S/D zones, and (c) the dopant of the first conductivity type is present in both S/D zones and has a concentration which locally reaches a main subsurface maximum concentration at a main subsurface maximum concentration location extending laterally below largely all of each of the channel and S/D zones, and (d) the main subsurface maximum concentration location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone wherein the concentration of the dopant of the first conductivity type (i) decreases by at least a factor of 10 in moving upward from the main subsurface maximum concentration location for each first FET along a selected vertical location for that first FET through a specified one of the S/D zones of that first FET to the body's upper surface, (ii) decreases substantially monotonically in moving from the main subsurface maximum concentration location for that first FET along the selected vertical location for that first FET to the pn junction for the specified S/D zone of that first FET, and (iii) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration for that second FET occurs at an additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of that second FET overlying its channel zone and at least part of each of its S/D zones, wherein the gate dielectric layers selectively satisfy at least two of the following gate dielectric layer requirements:
• a. the gate dielectric layer of one such first FET is of materially greater thickness than the gate dielectric layer of one such second FET;
• b. the gate dielectric layers of one such first FET and one such second FET are of approximately the same thickness;
• c. the gate dielectric layer of one such second FET is of materially greater thickness than the gate dielectric layer of one such first FET;
• d. the gate dielectric layer of one such first FET is of materially different thickness than the gate dielectric layer of another such first FET;
• and
• e. the gate dielectric layer of one such second FET is of materially different thickness than the gate dielectric layer of another such second FET.

A structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the FETs being provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, each FET comprising:

• a channel zone of a region of the body material;
• first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body-material region such that (a) each pn junction reaches a maximum depth below the body's upper surface, (b) the body-material region extends laterally under both S/D zones, and (c) the dopant of the first conductivity type is present in both S/D zones and has a concentration which locally reaches a main subsurface maximum concentration at a main subsurface maximum concentration location extending laterally below largely all of each of the channel and S/D zones, and (d) the main subsurface maximum concentration location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone wherein the concentration of the dopant of the first conductivity type (i) decreases by at least a factor of 10 in moving upward from the main subsurface maximum concentration location for each first FET along a selected vertical location for that first FET through a specified one of the S/D zones of that first FET to the body's upper surface, (ii) decreases substantially monotonically in moving from the main subsurface maximum concentration location for that first FET along the selected vertical location for that first FET to the pn junction for the specified S/D zone of that first FET, and (iii) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration for that second FET occurs at an additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of that second FET overlying its channel zone and at least part of each of its S/D zones, wherein there are multiple instances in which one first FET has a threshold voltage of materially lesser magnitude than one second FET and wherein the gate dielectric layers of the FETs in those instances selectively satisfy at least two of the following gate dielectric layer requirements:
• a. the gate dielectric layers of one such first FET and one such second FET are of approximately the same thickness;
• b. the gate dielectric layer of one such first FET is of materially greater thickness than the gate dielectric layer of one such second FET;
• and
• c. the gate dielectric layer of one such second FET is of materially greater thickness than the gate dielectric layer of that one such first FET.

A structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the FETs being provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, each FET comprising:

• a channel zone of a region of the body material;
• first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body-material region such that (a) each pn junction reaches a maximum depth below the body's upper surface, (b) the body-material region extends laterally under both S/D zones, and (c) the dopant of the first conductivity type is present in both S/D zones and has a concentration which locally reaches a main subsurface maximum concentration at a main subsurface maximum concentration location extending laterally below largely all of each of the channel and S/D zones, and (d) the main subsurface maximum concentration location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone wherein the concentration of the dopant of the first conductivity type (i) decreases by at least a factor of 10 in moving upward from the main subsurface maximum concentration location for each first FET along a selected vertical location for that first FET through a specified one of the S/D zones of that first FET to the body's upper surface, (ii) decreases substantially monotonically in moving from the main subsurface maximum concentration location for that first FET along the selected vertical location for that first FET to the pn junction for the specified S/D zone of that first FET, and (iii) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration for that second FET occurs at an additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of that second FET overlying its channel zone and at least part of each of its S/D zones, wherein there are multiple instances in which each S/D zone of an FET comprises a main S/D portion and a more lightly doped lateral S/D extension laterally continuous with the main S/D portion and extending laterally under the gate electrode of that FET such that its channel zone is terminated by its S/D extensions along the body's upper surface and wherein the S/D extensions of the FETs in those instances selectively satisfy at least two of the following S/D extension requirements:
• a. one of the S/D extensions of one such first FET extends deeper below the body's upper surface than the other of the S/D extensions of that first FET;
• b. each S/D extension of one such first FET extends materially deeper below the body's upper surface than each S/D extension of one such second FET;
• and
• c. each S/D extension of one such second FET extends materially deeper below the body's upper surface than each S/D extension of another such second FET.

A structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the FETs being provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, each FET comprising:

• a channel zone of a region of the body material;
• first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body-material region such that (a) each pn junction reaches a maximum depth below the body's upper surface, (b) the body-material region extends laterally under both S/D zones, and (c) the dopant of the first conductivity type is present in both S/D zones and has a concentration which locally reaches a main subsurface maximum concentration at a main subsurface maximum concentration location extending laterally below largely all of each of the channel and S/D zones, and (d) the main subsurface maximum concentration location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone wherein the concentration of the dopant of the first conductivity type (i) decreases by at least a factor of 10 in moving upward from the main subsurface maximum concentration location for each first FET along a selected vertical location for that first FET through a specified one of the S/D zones of that first FET to the body's upper surface, (ii) decreases substantially monotonically in moving from the main subsurface maximum concentration location for that first FET along the selected vertical location for that first FET to the pn junction for the specified S/D zone of that first FET, and (iii) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration for that second FET occurs at an additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of that second FET overlying its channel zone and at least part of each of its S/D zones, wherein there are multiple instances in which a pocket portion of the body-material region of an FET extends along its first S/D zone into its channel zone and is more heavily doped than laterally adjacent material of that body-material region and wherein the pocket portions of the FETs in those instances selectively satisfy at least two of the following pocket portion requirements:
• a. the pocket portion of one such first FET causes its channel zone to be asymmetric with respect to its S/D zones;
• b. another pocket portion of the body-material region of one such first FET extends along its second S/D zone into its channel zone and is more heavily doped than laterally adjacent material of that body-material region;
• and
• c. another pocket portion of the body-material region of one such second FET extends along its second S/D zone into its channel zone and is more heavily doped than laterally adjacent material of that body-material region.

A structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the FETs being provided along an upper surface of a semiconductor body having body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type, each FET comprising:

• a channel zone of a region of the body material;
• first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and being of a second conductivity type opposite to the first conductivity type so as to form respective pn junctions with the body-material region such that (a) each pn junction reaches a maximum depth below the body's upper surface, (b) the body-material region extends laterally under both S/D zones, and (c) the dopant of the first conductivity type is present in both S/D zones and has a concentration which locally reaches a main subsurface maximum concentration at a main subsurface maximum concentration location extending laterally below largely all of each of the channel and S/D zones, and (d) the main subsurface maximum concentration location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone;
• a gate dielectric layer overlying the channel zone;
• and
• a gate electrode overlying the gate dielectric layer above the channel zone wherein the concentration of the dopant of the first conductivity type (i) decreases by at least a factor of 10 in moving upward from the main subsurface maximum concentration location for each first FET along a selected vertical location for that first FET through a specified one of the S/D zones of that first FET to the body's upper surface, (ii) decreases substantially monotonically in moving from the main subsurface maximum concentration location for that first FET along the selected vertical location for that first FET to the pn junction for the specified S/D zone of that first FET, and (iii) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration for that second FET occurs at an additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of that second FET overlying its channel zone and at least part of each of its S/D zones, wherein the FETs selectively satisfy at least one of the following combinational requirements:
• a. one such first FET has a threshold voltage of materially lesser magnitude that one such second FET, and the gate dielectric layer of that first FET is of materially greater thickness than the gate dielectric layer of that second FET;
• b. one such first FET has a threshold voltage of materially lesser magnitude that one such second FET, and the gate dielectric layer of that first FET is of materially lesser thickness than the gate dielectric layer of that second FET;
• c. one such first FET has a threshold voltage of materially lesser magnitude that one such second FET, and the gate dielectric layers of those two first and second FETs are of materially greater thickness than the gate dielectric layer of another such FET;
• d. one such first FET has a threshold voltage of materially lesser magnitude that one such second FET, and the gate dielectric layers of those two first and second FETs are of materially lesser thickness than the gate dielectric layer of another such FET;
• e. one such first FET has a threshold voltage of materially lesser magnitude that each of two such second FETs whose respective threshold voltages differ materially in magnitude, and the gate dielectric layer of that first FET is of materially greater thickness than the gate dielectric layer of each of those second FETs;
• and
• f. one such first FET has a threshold voltage of materially lesser magnitude that each of two such second FETs whose respective threshold voltages differ materially in magnitude, and the gate dielectric layer of each those three FETs is of materially lesser thickness than the gate dielectric layer of another such FET.

A structure comprising a pair of opposite-polarity first and second field-effect transistors (“FETs”) provided along an upper surface of a semiconductor body, each FET comprising (i) a channel zone of body material of the semiconductor body, (ii) first and second source/drain (“S/D”) zones situated in the semiconductor body along its upper surface, laterally separated by the channel zone, and forming respective pn junctions with the body material such that each pn junction reaches a maximum depth below the body's upper surface and such that the body material extends laterally below both S/D zones, (iii) a gate dielectric layer overlying the channel zone, and (iv) a gate electrode overlying the gate dielectric layer above the channel zone wherein:

• the body material of the first FET is constituted with first body material doped with semiconductor dopant of a first conductivity type so as to be of the first conductivity type whereby the S/D zones of the first FET are of a second conductivity type opposite to the first conductivity type;
• the body material of the second FET is constituted with second body material doped with semiconductor dopant of the second conductivity type so as to be of the second conductivity type whereby the S/D zones of the second FET are of the first conductivity type;
• the dopant of the first conductivity type is also present in the S/D zones of the first FET and has a concentration which (a) locally reaches a subsurface concentration maximum at a first subsurface body-material location extending laterally below largely all of each of the channel and S/D zones of the first FET, (b) decreases by at least a factor of 10 in moving upward from the first subsurface body-material location along a selected first vertical location through a specified one of the S/D zones of the first FET to the body's upper surface, and (c) decreases substantially monotonically and substantially inflectionlessly in moving from the first subsurface body-material location along the selected first vertical location to the pn junction for the specified S/D zone of the first FET;
• the first subsurface body-material location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for the specified S/D zone of the first FET;
• the dopant of the second conductivity type is also present in the S/D zones of the second FET and has a concentration which (a) locally reaches a subsurface concentration maximum at a second subsurface body-material location extending laterally below largely all of each of the channel and S/D zones of the second FET and (b) decreases by less than a factor of 10 in moving upward from the second subsurface body-material location along any vertical location through each S/D zone of the second FET to the body's upper surface;
• and
• the second subsurface body-material location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone of the second FET.

A method of fabricating a semiconductor structure, the method comprising:

• introducing semiconductor dopant of a first conductivity type into a pair of portions of a semiconductor body to define first and second well regions such that each well region is of the first conductivity type;
• and
• introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into a pair of portions of the semiconductor body to respectively define first and second zones of the second conductivity type such that, upon completion of fabrication of the structure, (a) the first and second well regions respectively forms first and second pn junctions respectively with, and respectively extend laterally below, the first and second zones, (b) each pn junction extends to a maximum depth below an upper surface of the semiconductor body, (c) semiconductor dopant of the first conductivity type is present in both zones, (d) all semiconductor dopant of the first conductivity type in the semiconductor body has a concentration which locally reaches first and second subsurface maximum concentrations at respective first and second subsurface maximum concentration locations situated respectively in the first and second well regions and respectively extending laterally below the first and second zones, (e) the first and second subsurface maximum concentration locations occur no more than 10 times deeper below the body's upper surface respectively than the maximum depths of the first and second pn junctions, (f) the concentration of all dopant of the first conductivity type (i) decreases by at least a factor of 10 in moving upward from the first subsurface maximum concentration location along a selected first vertical location through the first zone to the body's upper surface, (ii) decreases substantially monotonically by less than a factor of 10 in moving from the first subsurface maximum concentration location along the first vertical location to the first pn junction, and (iii) reaches at least one additional subsurface maximum concentration in moving upward from the second subsurface maximum concentration location along a selected second vertical location through the second zone to the body's upper surface.

A method of fabricating a structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the method comprising:

• introducing semiconductor dopant of a first conductivity type into a like plurality of body-material regions of a semiconductor body such that each body-material region is of the first conductivity type wherein the body-material regions comprise at least one first body-material region, each intended for one corresponding first FET, and at least one second body-material region, each intended for one corresponding second FET;
• defining a like plurality of gate electrodes respectively for the FETs such that (a) the gate electrode of each first FET is situated above, and vertically separated by a corresponding dielectric layer from, part of one corresponding first body-material region intended to be a channel zone for that first FET and (b) the gate electrode of each second FET is situated above, and vertically separated by a corresponding dielectric layer from, part of one corresponding second body-material region intended to be a channel zone for that second FET;
• and
• introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into portions of the semiconductor body to form, for each FET, a pair of source/drain (“S/D”) zones of the second conductivity type laterally separated by that FET's channel zone such that, upon completion of fabrication of the structure, (a) each body-material region forms a pair of pn junctions respectively with, and extends laterally below, the S/D zones of the corresponding FET, (b) each pn junction extends to a maximum depth below an upper surface of the semiconductor body, (c) semiconductor dopant of the first conductivity type is present in each S/D zone, (d) all semiconductor dopant of the first conductivity type in the semiconductor body has a concentration which, for each first FET, reaches a corresponding first main subsurface maximum concentration at a corresponding first main subsurface maximum concentration location below the body's upper surface and which, for each second FET, reaches a corresponding second main subsurface maximum concentration at a corresponding second main subsurface maximum concentration location below the body's upper surface, (e) each main subsurface maximum concentration location extends laterally below largely all of each of the channel and S/D zones of the corresponding FET and occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone of that FET, and (f) the concentration of all dopant of the first conductivity type (f1) decreases by at least a factor of 10 in moving upward from each first main subsurface maximum concentration location along a selected vertical location through a specified one of the S/D zones of the corresponding first FET to the body's upper surface, (f2) decreases substantially monotonically by less than a factor of 10 in moving from that first main subsurface maximum concentration location along that selected vertical location to the pn junction for the specified S/D zone of the corresponding first FET, and (f3) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration occurs at a corresponding additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of the corresponding second FET overlying its channel zone and at least part of each of its S/D zones.

A method of fabricating a structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the method comprising:

• introducing semiconductor dopant of a first conductivity type into a like plurality of body-material regions of a semiconductor body such that each body-material region is of the first conductivity type wherein the body-material regions comprise at least one first body-material region, each intended for one corresponding first FET, and at least one second body-material region, each intended for one corresponding second FET;
• defining a like plurality of gate electrodes respectively for the FETs such that (a) the gate electrode of each first FET is situated above, and vertically separated by a corresponding gate dielectric layer from, part of one corresponding first body-material region intended to be a channel zone for that first FET and (b) the gate electrode of each second FET is situated above, and vertically separated by a corresponding gate dielectric layer from, part of one corresponding second body-material region intended to be a channel zone for that second FET;
• and
• introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into portions of the semiconductor body to form, for each FET, a pair of source/drain (“S/D”) zones of the second conductivity type laterally separated by that FET's channel zone such that, upon completion of fabrication of the structure, (a) each body-material region forms a pair of pn junctions respectively with, and extends laterally below, the S/D zones of the corresponding FET, (b) each pn junction extends to a maximum depth below an upper surface of the semiconductor body, (c) semiconductor dopant of the first conductivity type is present in each S/D zone, (d) all semiconductor dopant of the first conductivity type in the semiconductor body has a concentration which, for each first FET, reaches a corresponding first main subsurface maximum concentration at a corresponding first main subsurface maximum concentration location below the body's upper surface and which, for each second FET, reaches a corresponding second main subsurface maximum concentration at a corresponding second main subsurface maximum concentration location below the body's upper surface, (e) each main subsurface maximum concentration location extends laterally below largely all of each of the channel and S/D zones of the corresponding FET and occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone of that FET, and (f) the concentration of all dopant of the first conductivity type (f1) decreases by at least a factor of 10 in moving upward from each first main subsurface maximum concentration location along a selected vertical location through a specified one of the S/D zones of the corresponding first FET to the body's upper surface, (f2) decreases substantially monotonically in moving from that first main subsurface maximum concentration location along that selected vertical location to the pn junction for the specified S/D zone of the corresponding first FET, and (f3) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration occurs at a corresponding additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of the corresponding second FET overlying its channel zone and at least part of each of its S/D zone wherein the gate dielectric layers are formed so as to selectively satisfy at least two of the following gate dielectric layer requirements:
• a. the gate dielectric layer of one such first FET is of materially greater thickness than the gate dielectric layer of one such second FET;
• b. the gate dielectric layers of one such first FET and one such second FET are of approximately the same thickness;
• c. the gate dielectric layer of one such second FET is of materially greater thickness than the gate dielectric layer of one such first FET;
• d. the gate dielectric layer of one such first FET is of materially different thickness than the gate dielectric layer of another such first FET;
• and
• e. the gate dielectric layer of one such second FET is of materially different thickness than the gate dielectric layer of another such second FET.

A method of fabricating a structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the method comprising:

• introducing semiconductor dopant of a first conductivity type into a like plurality of body-material regions of a semiconductor body such that each body-material region is of the first conductivity type wherein the body-material regions comprise at least one first body-material region, each intended for one corresponding first FET, and at least one second body-material region, each intended for one corresponding second FET;
• defining a like plurality of gate electrodes respectively for the FETs such that (a) the gate electrode of each first FET is situated above, and vertically separated by a corresponding dielectric layer from, part of one corresponding first body-material region intended to be a channel zone for that first FET and (b) the gate electrode of each second FET is situated above, and vertically separated by a corresponding dielectric layer from, part of one corresponding second body-material region intended to be a channel zone for that second FET;
• and
• introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into portions of the semiconductor body to form, for each FET, a pair of source/drain (“S/D”) zones of the second conductivity type laterally separated by that FET's channel zone such that, upon completion of fabrication of the structure, (a) each body-material region forms a pair of pn junctions respectively with, and extends laterally below, the S/D zones of the corresponding FET, (b) each pn junction extends to a maximum depth below an upper surface of the semiconductor body, (c) semiconductor dopant of the first conductivity type is present in each S/D zone, (d) all semiconductor dopant of the first conductivity type in the semiconductor body has a concentration which, for each first FET, reaches a corresponding first main subsurface maximum concentration at a corresponding first main subsurface maximum concentration location below the body's upper surface and which, for each second FET, reaches a corresponding second main subsurface maximum concentration at a corresponding second main subsurface maximum concentration location below the body's upper surface, (e) each main subsurface maximum concentration location extends laterally below largely all of each of the channel and S/D zones of the corresponding FET and occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone of that FET, and (f) the concentration of all dopant of the first conductivity type (f1) decreases by at least a factor of 10 in moving upward from each first main subsurface maximum concentration location along a selected vertical location through a specified one of the S/D zones of the corresponding first FET to the body's upper surface, (f2) decreases substantially monotonically in moving from that first main subsurface maximum concentration location along that selected vertical location to the pn junction for the specified S/D zone of the corresponding first FET, and (f3) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration occurs at a corresponding additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of the corresponding second FET overlying its channel zone and at least part of each of its S/D zone, wherein the act of introducing the dopant of the second conductivity type entails defining the S/D zones so that, upon completion of fabrication of the structure, there are multiple instances in which each S/D zone of an FET comprises a main S/D portion and a more lightly doped lateral S/D extension laterally continuous with the main S/D portion and extending laterally under the gate electrode of that FET such that its channel zone is terminated by its S/D extensions along the body's upper surface and wherein the S/D extensions of the FETs in those instances selectively satisfy at least two of the following S/D extension requirements:
• a. one of the S/D extensions of one such first FET extends deeper below the body's upper surface than the other of the S/D extensions of that first FET;
• b. each S/D extension of one such first FET extends materially deeper below the body's upper surface than each S/D extension of one such second FET;
• and
• c. each S/D extension of one such second FET extends materially deeper below the body's upper surface than each S/D extension of another such second FET.

A method of fabricating a structure comprising a plurality of like-polarity field-effect transistors (“FETs”) including at least one first FET and at least one second FET, the method comprising:

• introducing semiconductor dopant of a first conductivity type into a like plurality of body-material regions of a semiconductor body such that each body-material region is of the first conductivity type wherein the body-material regions comprise at least one first body-material region, each intended for one corresponding first FET, and at least one second body-material region, each intended for one corresponding second FET;
• defining a like plurality of gate electrodes respectively for the FETs such that (a) the gate electrode of each first FET is situated above, and vertically separated by a corresponding dielectric layer from, part of one corresponding first body-material region intended to be a channel zone for that first FET and (b) the gate electrode of each second FET is situated above, and vertically separated by a corresponding dielectric layer from, part of one corresponding second body-material region intended to be a channel zone for that second FET;
• introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into portions of the semiconductor body to form, for each FET, a pair of source/drain (“S/D”) zones of the second conductivity type laterally separated by that FET's channel zone such that, upon completion of fabrication of the structure, (a) each body-material region forms a pair of pn junctions respectively with, and extends laterally below, the S/D zones of the corresponding FET, (b) each pn junction extends to a maximum depth below an upper surface of the semiconductor body, (c) semiconductor dopant of the first conductivity type is present in each S/D zone, (d) all semiconductor dopant of the first conductivity type in the semiconductor body has a concentration which, for each first FET, reaches a corresponding first main subsurface maximum concentration at a corresponding first main subsurface maximum concentration location below the body's upper surface and which, for each second FET, reaches a corresponding second main subsurface maximum concentration at a corresponding second main subsurface maximum concentration location below the body's upper surface, (e) each main subsurface maximum concentration location extends laterally below largely all of each of the channel and S/D zones of the corresponding FET and occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone of that FET, and (f) the concentration of all dopant of the first conductivity type (f1) decreases by at least a factor of 10 in moving upward from each first main subsurface maximum concentration location along a selected vertical location through a specified one of the S/D zones of the corresponding first FET to the body's upper surface, (f2) decreases substantially monotonically in moving from that first main subsurface maximum concentration location along that selected vertical location to the pn junction for the specified S/D zone of the corresponding first FET, and (f3) reaches at least one additional subsurface maximum concentration between the body's upper surface and the main subsurface maximum concentration location for each second FET such that each additional subsurface maximum concentration occurs at a corresponding additional subsurface maximum concentration location extending laterally below largely all material of the gate electrode of the corresponding second FET overlying its channel zone and at least part of each of its S/D zone;
• and
• introducing additional semiconductor dopant of the first conductivity type into portions of the semiconductor body to define pocket portions of the body-material regions so that, upon completion of fabrication of the structure, there are multiple instances in which a pocket portion of the body-material region of an FET extends along its first S/D zone into its channel zone and is more heavily doped than laterally adjacent material of that body-material region, wherein the pocket portions of the FETs in those instances selectively satisfy at least two of the following pocket portion requirements:
• a. the pocket portion of one such first FET causes its channel zone to be asymmetric with respect to its S/D zones;
• b. another pocket portion of the body-material region of one such first FET extends along its second S/D zone into its channel zone and is more heavily doped than laterally adjacent material of that body-material region;
• and
• c. another pocket portion of the body-material region of one such second FET extends along its second S/D zone into its channel zone and is more heavily doped than laterally adjacent material of that body-material region

A method of fabricating a pair of opposite-polarity first and second field-effect transistors (“FETs”), the method comprising:

• introducing (i) first semiconductor dopant of a first conductivity type into first body material of a semiconductor body such that the first body material is of the first conductivity type and (ii) first semiconductor dopant of a second conductivity type opposite to the first conductivity type into second body material of the semiconductor body such that the second body material is of the second dopant conductivity type;
• defining a pair of gate electrodes respectively for the FETs such that the gate electrodes are situated above, and vertically separated by a pair of respective gate dielectric layers from, a pair of parts of the first and second body materials intended to be a pair of respective channel zones for the first and second FETs;
• and
• introducing (i) second semiconductor dopant of the second conductivity type into the semiconductor body to form, for the first FET, a pair of source/drain (“S/D”) zones of the second conductivity type laterally separated by the channel zone of the first FET and (ii) second semiconductor dopant of the first conductivity type into the semiconductor body to form, for the second FET, a pair of S/D zones of the first conductivity type laterally separated by the channel zone of the second FET such that, upon completion of fabrication of the FETs, (a) the first body material forms a pair of pn junctions respectively with the S/D zones of the first FET and extends laterally below its S/D zones, (b) the second body material forms a pair of pn junctions respectively with the S/D zones of the second FET and extends laterally below its S/D zones, (c) each pn junction thereby extends to a maximum depth into the semiconductor body below its upper surface, (c) the first dopant of the first conductivity type is also present in the S/D zones of the first FET and has a concentration which locally reaches a subsurface concentration maximum at a first subsurface body-material location extending laterally below largely all of each of the channel and S/D zones of the first FET, decreases by at least a factor of 10 in moving upward from the first subsurface body-material location along a selected first vertical location through a specified one of the S/D zones of the first FET to the body's upper surface, and decreases substantially monotonically and substantially inflectionlessly in moving from the first subsurface body-material location along the selected first vertical location to the pn junction for the specified S/D zone of the first FET, (d) the first subsurface body-material location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for the specified S/D zone of the first FET, (e) the first dopant of the second conductivity type is also present in the S/D zones of the second FET and has a concentration which locally reaches a subsurface concentration maximum at a second subsurface body-material location extending laterally below largely all of each of the channel and S/D zones of the second FET and decreases by less than a factor of 10 in moving upward from the second subsurface body-material location along any vertical location through each S/D zone of the second FET to the body's upper surface, and (f) the second subsurface body-material location occurs no more than 10 times deeper below the body's upper surface than the maximum depth of the pn junction for each S/D zone of the second FET.