Structure and Method for Forming a Salicide on the Gate Electrode of a Trench-Gate FET

A method of forming a trench-gate FET structure, the method comprising:

• forming a trench extending into the semiconductor region;
• forming a gate dielectric along sidewalls of the trench and over mesa surfaces of the semiconductor region adjacent to the trench;
• forming a gate electrode in the trench;
• performing a first implant of dopants of the first conductivity type into the semiconductor region;
• performing a second implant of dopants of a second conductivity type into the semiconductor region;
• performing one or more thermal processes to thereby form a source region corresponding to the first implant and a well region corresponding to the second implant, the one or more thermal processes being performed substantially without oxygen to minimize oxide formation over the gate electrode;
• and
• after performing the thermal process, forming a salicide layer comprising at least one of cobalt or nickel over the gate electrode abutting portions of the gate dielectric, wherein the gate dielectric prevents formation of the salicide layer along the mesa surfaces of the semiconductor region.

A trench-gate FET structure comprising:

• trenches extending into a semiconductor region, wherein portions of the semiconductor region extending between adjacent trenches form mesa surfaces;
• a continuous gate dielectric extending along sidewalls of each trench and over the mesa surfaces;
• a gate electrode in each trench;
• a salicide layer comprising at least one of cobalt or nickel extending over the gate electrode in each trench and abutting portions of the gate dielectric;
• a dielectric layer over the salicide layer in each trench;
• and
• an interconnect layer over the dielectric layer and over portions of the gate dielectric extending over the mesa surfaces.