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US 2010/0244122 A1Published application
Memory utilizing oxide nanolaminates
AssigneeMicron Technology, Inc.
InventorsLeonard Forbes, Kie Y. Ahn
Life of this patent
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Abstract
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.
Claims18
A transistor, comprising:
- a first source/drain region;
- a second source/drain region;
- a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator;
- and
- wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous.
2 more elements
A vertical memory cell, comprising:
- a vertical transistor extending outwardly from a substrate, the vertical transistor having a source region, a drain region, a channel region between the source region and the drain region, and a gate, separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous;
- a control line coupled to the gate;
- a first transmission line formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the first transmission line;
- and
- a second transmission line coupled to the drain region.
2 more elements
A vertical memory cell, comprising:
- a vertical transistor extending outwardly from a substrate, the vertical transistor having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes nanolaminate charge trapping layers, wherein at least one charge trapping layer is substantially amorphous, at least one nanolaminate layer formed using atomic layer deposition techniques;
- a control line coupled to the gate;
- a first transmission line formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the first transmission line;
- and
- a second transmission line coupled to the drain region.
2 more elements
A transistor array, comprising:
- a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, and wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous;
- a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array;
- a number of control lines coupled to the gate of each transistor cell along columns of the transistor array;
- and
- a number of first transmission lines, wherein the first source/drain region of each transistor cell is coupled to the number of first transmission lines along rows of the transistor cells.
2 more elements
A method for forming a transistor device, comprising:
- forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate;
- forming a multilayer gate insulator opposing the channel region, wherein forming the multilayer gate insulator includes forming a plurality of monolayers using atomic layer deposition, wherein at least one monolayer is substantially amorphous;
- and
- forming a gate over the multilayer gate insulator.
1 more element
A vertical memory cell, comprising:
- a vertical transistor extending outwardly from a substrate, the vertical transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, wherein the multilayer gate insulator includes at least one amorphous charge trapping nanolaminate layer formed using atomic layer deposition techniques;
- a first transmission line coupled to the first source/drain region;
- and
- a second transmission line coupled to the second source/drain region.
1 more element
Dependencies are inferred from the claim text.