Semiconductor device

A semiconductor device, comprising:

• a semiconductor substrate including a first region and a second region;
• a plurality of vertical pillar transistors formed in the first region of the semiconductor substrate, the plurality of vertical pillar transistors each comprising a pillar, a first gate insulation layer provided on a sidewall surface of the pillar, a first gate electrode provided on the first gate insulation layer, an impurity region provided in an upper portion of the pillar which protrudes from the first gate electrode;
• a plurality of planar type transistors provided on an upper surface of the substrate in the second region of the substrate;
• wherein each of the planar type transistors includes a second gate structure having a second gate insulation layer pattern, a second gate electrode, a mask pattern stacked on a surface of the substrate in the second region, and a source/drain under a surface of the substrate in both sides of the second gate structure;
• an upper insulation interlayer pattern formed on the first region and the second region in the substrate, wherein the upper insulation layer pattern covers the planar type transistors in the second region and exposes upper surfaces of the pillars in the first region through an opening in the upper insulation interlayer pattern and wherein an upper surface of the upper insulation interlayer pattern in the second region is substantially higher than an upper surface of the impurity region in the upper portion of the pillar in the first region of the substrate;
• a first wiring penetrating the upper insulation interlayer pattern and electrically connected to an end portion of the first gate electrode of the vertical pillar transistor,
• a second wiring penetrating the upper insulation interlayer pattern and electrically connected to the second gate electrode;
• a third wiring penetrating the upper insulation interlayer pattern and electrically connected to the source/drain;
• and
• a capacitor electrically connected to the impurity region of the vertical pillar transistor in the first region of the substrate, wherein the capacitor includes a lower electrode which directly contacts the impurity region in the upper portion of the pillar exposed by the upper insulation interlayer pattern, a dielectric layer formed on substantially an entire outer surface of the lower electrode and an upper electrode formed on the dielectric layer.