Trenched metal-oxide-semiconductor device and fabrication thereof
AssigneeNiko Semiconductor Co., Ltd.
InventorHsiu Wen HSU
Life of this patent
Estimating the term…
Abstract
A fabrication method of a trenched metal-oxide-semiconductor device is provided. After the formation of the gate dielectric layer, a first poly-silicon layer is deposited along the profile of the gate trench. Then, impurities of first conductivity type are implanted to the first poly-silicon layer at the bottom of the gate trench. Then, a second poly-silicon layer with second conductivity type is deposited over the first poly-silicon layer. The impurities in the first poly-silicon layer and the second poly-silicon layer are then driven by an annealing step to form a first doping region with first conductivity type located at the bottom of the gate trench and a second doping region with second conductivity type.
Claims14
A fabrication method of a trench metal-oxide-semiconductor comprising:
- providing a substrate;
- forming an epitaxial layer on the substrate;
- forming at least one gate trench in the epitaxial layer;
- forming a gate dielectric layer on inner walls of the gate trench;
- depositing a first poly-silicon layer along surface profile of the inner walls of the gate trench;
- implanting impurities of first conductivity type to the first poly-silicon layer adjacent to the bottom of the gate trench;
- depositing a second poly-silicon layer with impurities of second conductivity type over the first poly-silicon layer;
- and
- annealing the first poly-silicon layer and the second poly-silicon layer to diffuse the impurities therein to form a first doping region of the first conductivity type and a second doping region of the second conductivity type, wherein the first doping region is located at the bottom of the gate trench and an PN junction capacitor is formed between the first doping region and the second doping region.
A trench metal-oxide-semiconductor device comprising:
- a substrate;
- an epitaxial layer, formed on the substrate;
- at least one gate trench, located in the epitaxial layer;
- a gate dielectric layer, located on inner walls of the gate trench;
- and
- a poly-silicon gate, having a first doping region of first conductivity type and a second doping region of second conductivity type, wherein the first doping region is located at the bottom of the gate trench, the second doping region is located on the first doping region, and an PN junction capacitor is formed between the first doping region and the second doping region.
Dependencies are inferred from the claim text.