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US 2010/0244034 A1Published application
Thin film transistor
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHidekazu Miyairi
Life of this patent
Estimating the term…
Abstract
A thin film transistor includes a gate electrode; a gate insulating layer which is provided to cover the gate electrode; a semiconductor layer which is provided over the gate insulating layer to overlap with the gate electrode; an impurity semiconductor layer which is partly provided over the semiconductor layer and which forms a source region and a drain region; and a wiring layer which is provided over the impurity semiconductor layer, where a width of the source region and the drain region is narrower than a width of the semiconductor layer, and where the width of the semiconductor layer is increased at least in a portion between the source region and the drain region.
Claims18
A thin film transistor comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer which is provided over the gate insulating layer to overlap with the first wiring layer;
- an impurity semiconductor layer which is partly provided over the semiconductor layer and forms a source region and a drain region;
- and
- a second wiring layer over the impurity semiconductor layer,
- wherein the semiconductor layer includes a first region having a first width and a second region having a second width, the second width being larger than the first width, and
- wherein the second region is provided at least in a portion between the source region and the drain region.
5 more elements
A thin film transistor comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer which is provided over the gate insulating layer to overlap with the first wiring layer;
- an impurity semiconductor layer which is partly provided over the semiconductor layer and forms a source region and a drain region;
- and
- a second wiring layer over the impurity semiconductor layer,
- wherein the semiconductor layer includes a first region having a first width and a second region having a second width, the second width being larger than the first width, and
- wherein the second region is provided only in a portion between the source region and the drain region.
5 more elements
A thin film transistor comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer which is provided over the gate insulating layer to overlap with the first wiring layer;
- an impurity semiconductor layer which is partly provided over the semiconductor layer and forms a source region and a drain region;
- and
- a second wiring layer over the impurity semiconductor layer,
- wherein the semiconductor layer includes a first region having a first width and a second region having a second width, the second width being larger than the first width,
- wherein the second region is provided at least in a portion between the source region and the drain region, and
- wherein a length between the source region and the drain region is shorter than a length of the second region.
6 more elements
A display device comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer which is provided over the gate insulating layer to overlap with the first wiring layer;
- an impurity semiconductor layer which is partly provided over the semiconductor layer and forms a source region and a drain region;
- and
- a second wiring layer over the impurity semiconductor layer,
- wherein the semiconductor layer includes a first region having a first width and a second region having a second width, the second width being larger than the first width,
- wherein the second region is provided at least in a portion between the source region and the drain region, and
- wherein the second wiring layer is provided over the source region and the drain region, and a pixel electrode layer which is selectively formed is connected to the second wiring layer.
6 more elements
A display device comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer which is provided over the gate insulating layer to overlap with the first wiring layer;
- an impurity semiconductor layer which is partly provided over the semiconductor layer and forms a source region and a drain region;
- and
- a second wiring layer over the impurity semiconductor layer,
- wherein the semiconductor layer includes a first region having a first width and a second region having a second width, the second width being larger than the first width,
- wherein the second region is provided only in a portion between the source region and the drain region, and
- wherein the second wiring layer is provided over the source region and the drain region, and a pixel electrode layer which is selectively formed is connected to the second wiring layer.
6 more elements
A display device comprising:
- a first wiring layer;
- a gate insulating layer covering the first wiring layer;
- a semiconductor layer over the gate insulating layer to overlap with the first wiring layer;
- an impurity semiconductor layer which is partly provided over the semiconductor layer and forms a source region and a drain region;
- and
- a second wiring layer over the impurity semiconductor layer,
- wherein the semiconductor layer includes a first region having a first width and a second region having a second width, the second width being larger than the first width,
- wherein the second region is provided at least in a portion between the source region and the drain region,
- wherein a length between the source region and the drain region is shorter than a length of the second region, and
- wherein the second wiring layer is provided over the source region and the drain region, and a pixel electrode layer which is selectively formed is connected to the second wiring layer.
7 more elements
Dependencies are inferred from the claim text.