Process for manufacturing a wafer by annealing of buried channels
AssigneeSTMicroelectronics S.r.l.
InventorsFlavio VILLA, Gabriele Barlocchi, Pietro Corona
Life of this patent
Estimating the term…
Abstract
A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
Claims19
-32. (canceled)
A method, comprising:
- forming an opening in a region of a semiconductor layer;
- forming an epitaxial layer on the semiconductor layer;
- and
- converting the opening into a cavity encapsulated by semiconductor material, wherein converting the opening into a cavity includes annealing the region.
The method of claim 40 wherein forming an opening includes removing material.
The method of claim 40 wherein forming an epitaxial layer further comprises:
- closing the opening to form the cavity, and
- annealing the region after closing the opening.
The method of claim 42 wherein:
- after growing the epitaxial layer but before annealing the region, the cavity has a first shape, and
- after annealing the region, the cavity has a second shape that is different than the first shape.
The method of claim 42 wherein growing the epitaxial layer includes growing the layer in a deoxidizing atmosphere.
The method of claim 42 wherein growing the epitaxial layer includes growing the layer in an atmosphere having a high concentration of hydrogen.
The method of claim 40 wherein annealing the region includes annealing the region in a deoxidizing atmosphere.
The method of claim 40 further comprising disposing a circuit component in the region and adjacent the cavity, the component operable to generate a signal.
A semiconductor structure, comprising:
- a closed cavity;
- and
- an epitaxial layer disposed over the cavity.
The semiconductor structure of claim 48 wherein the closed cavity has a shape that includes a substantially circular cross-section.
The semiconductor structure of claim 48 wherein the epitaxial layer surrounds the closed cavity.
A semiconductor structure, comprising:
- a region;
- a cavity disposed in the region and formed by
- forming an opening in the region, and
- annealing the region;
- and
- an epitaxial layer disposed over the cavity.
The semiconductor structure of claim 51 further comprising a circuit component disposed in the region and adjacent the cavity, the component operable to generate a signal.
The semiconductor structure of claim 51 wherein forming the cavity includes growing an epitaxial layer to close the cavity before annealing the region.
A system, comprising:
- a first integrated circuit, comprising
- a semiconductor structure, comprising:
- a closed cavity;
- and
- an epitaxial layer disposed over the cavity.
- a second integrated circuit coupled to the first integrated circuit.
The system of claim 54 wherein the first and second integrated circuits are disposed on a same die.
The system of claim 54 wherein the first and second integrated circuits are disposed on respective dies.
The system of claim 54 wherein the second integrated circuit comprises a controller.
Dependencies are inferred from the claim text.