Frequency divider, frequency synthesizer and application circuit

A frequency synthesizer comprising:

• a phase-locked loop (PLL) configured to provide an oscillation frequency signal in response to a reference frequency signal and each of plurality of division frequency signals, wherein the PLL comprises a frequency divider having a prescaler, and a plurality of modulus dividers commonly coupled to the prescaler and configured to provide the plurality of division frequency signals;
• a sigma-delta modulator configured to operate in synchronization with one of the plurality of division frequency signals, and sigma-delta modulate a clock signal and data to provide a modulation signal;
• and
• a delay unit configured to delay the modulation signal to provide control signals to the PLL.

An application circuit comprising:

• a data processing unit configured to process baseband data and convert the processed baseband data to an amplitude signal and a phase signal;
• a frequency synthesizer configured to generate an oscillation frequency signal based on a reference frequency signal and the phase signal;
• and
• a power amplifier configured to synthesize the oscillation frequency signal and the amplitude signal to output a transmission signal,
• wherein the frequency synthesizer comprises a phase-lock loop (PLL) configured to provide the oscillation frequency signal in response to the reference frequency signal and each of a plurality of division frequency signals, the PLL comprising a frequency divider having a prescaler and a plurality of modulus divider commonly coupled to the prescaler and configured to provide the plurality of division frequency signals.