Digital signal processor (dsp) with vector math instruction
AssigneeTexas Instruments Incorporated
InventorUdayan DASGUPTA
Life of this patent
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Abstract
In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. A vector math instruction decoded by the instruction decode unit causes input vectors and output vectors to be aligned with a maximum boundary of the register set and causes parallel operations by the work units.
Claims20
A digital signal processor (DSP), comprising:
- an instruction fetch unit;
- an instruction decode unit in communication with the instruction fetch unit;
- and
- a register set and a plurality of work units in communication with the instruction decode unit,
- wherein a vector math instruction decoded by the instruction decode unit causes input vectors and output vectors to be aligned with a maximum boundary of the register set and causes parallel operations by said work units.
A method for a digital signal processor (DSP) with a register set and work units, the method comprising;
- decoding a vector math instruction;
- in response to decoding the vector math instruction, aligning input vectors and output vectors with a maximum boundary of the register set;
- and
- in response to decoding the vector math instruction, performing parallel operations with the register set and work units to complete a math function.
Dependencies are inferred from the claim text.