Reconfigurable logic cell made up of double-gate mosfet transistors

A reconfigurable logic cell comprising n inputs (A,B, . . . ), n being greater than or equal to 2, and capable of producing at least four logic functions with which logic signals provided on the n inputs (A,B, . . . ) may be processed, characterized in that it comprises, between the ground and the output (F) of the cell, at least one first branch including n dual gate N type MOSFET transistors (M1,M2, . . . ) in series and n−1 branches in parallel with the first branch, each provided with one dual gate N type MOSFET transistor (M3), each of the logic functions corresponding to a given configuration of the cell wherein a specific set of control signals (C1,C2, . . . ) is applied on the rear gates of at least one portion of the transistors (M2,M3, . . . ), each control signal (C1,C2, . . . ) being capable of setting the transistor (M2,M3, . . . ) to a particular operating mode, the n inputs (A,B, . . . ) being each connected on the front gate of one of the n transistors (M1,M2, . . . ) of the first branch, n−1 inputs (B) being also applied on the front gate of one (M3) of the n−1 transistors of the n−1 branches in parallel with the first branch.