Microcomputer and dividing circuit

A microcomputer formed on a single semiconductor device comprising:

• a CPU having general purpose registers and a program counter;
• and
• a memory coupled to said CPU,
• wherein the CPU is capable of processing a data transfer instruction, a conditional branch instruction and an unconditional branch instruction,
• wherein each of the data transfer instruction, the conditional branch instruction and the unconditional branch instruction is of 16 bits in length,
• wherein the memory stores instructions to be processed by said CPU,
• wherein the conditional branch instruction includes a first area for a first displacement,
• wherein the unconditional branch instruction includes a second area for a second displacement,
• wherein a length of the first area of the conditional branch instruction is smaller than that of the unconditional branch instruction,
• wherein the data transfer instruction includes a third area for a third displacement and a fourth area for destination register information to designate the general purpose registers where source data is to be loaded,
• wherein a first branch target address of the conditional branch instruction is obtained based on the first displacement in the first area of the conditional branch instruction and an address in the program counter,
• wherein a second branch target address of the unconditional branch instruction is obtained based on the second displacement in the second area of the unconditional branch instruction and an address in the program counter, and
• wherein 32 bits of the source data is obtained from a memory location indicated by an address obtained based on the third displacement in the third area of the data transfer instruction and an address in the program counter, and the source data is loaded into one of the general purpose registers which is designated by the fourth area of the data transfer instruction.

A central processing unit of RISC architecture on a semiconductor chip and adapted to execute a data transfer instruction, the central processing unit comprising:

• a program counter;
• a plurality of registers;
• wherein the data transfer instruction is of 16 bits in length and includes:
• a first field to indicate an operation code for a data transfer operation,
• a second field to indicate a destination register which is one of the plurality of registers where data of a bit length greater than the 16 bit length is to be loaded, and
• a third field to indicate a displacement which is utilized for indicating a first address by adding to a second address in the program counter,
• wherein the central processing unit executes the data transfer instruction to load the data of a bit length greater than the 16 bits in length stored in the first address to the destination register.

A data processor on a single semiconductor device, comprising:

• a RISC type CPU to have 32-bit general purpose registers and a program counter;
• and
• a memory coupled to the CPU and to store instructions to be executed by the RISC type CPU,
• wherein the instructions include a data transfer instruction of 16 bits in length and include:
• a first area to indicate an operation code for a data transfer operation,
• a second area to indicate a destination register which is one of the 32-bit general purpose registers where data of 32 bits in length is to be loaded, and
• a third area to indicate a first displacement which is used for indicating a first address by adding to a second address in the program counter,
• wherein the RISC type CPU executes the data transfer instruction to load the data stored in the first address to the destination register.

A microcomputer on a single semiconductor device comprising:

• a CPU having general purpose registers and a program counter;
• a RAM coupled to the CPU;
• a DMA controller coupled to the RAM;
• and
• a memory coupled to the CPU and for storing instructions to be processed by the CPU;
• wherein the instructions include:
• a conditional branch instruction of 16 bits in length and including a first area for a first displacement which is utilized for indicating a first branch target address by adding to a second address in the program counter,
• an unconditional branch instruction of 16 bits in length and including a second area for a second displacement which is utilized for indicating a second branch target address by adding to the second address in the program counter and whose length is longer than that of the first area, and
• a data transfer instruction of 16 bits in length and including a third area for a third displacement which is utilized for indicating a first address by adding to the second address in the program counter and a fourth area for a destination register information for designating one of the general purpose registers where data of 32 bits in length which is stored in the first address is loaded.

A central processing unit of RISC architecture on a semiconductor chip and adapted to execute a data transfer instruction, the central processing unit comprising:

• a program counter;
• and
• a plurality of registers,
• wherein the data transfer instruction is of 16 bits in length and includes:
• a first field to indicate an operation code for a data transfer operation,
• a second field to indicate a destination register which is one of the plurality of registers, data of a bit length being greater than the 16 bit length to be loaded in to the destination register, and
• a third field to indicate a first displacement which is utilized for indicating a first address by adding to a second address in the program counter,
• wherein the central processing unit executes the data transfer instruction to load the data stored in the first address to the destination register.