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US 2010/0187528 A1Published application
Guard ring extension to prevent reliability failures
AssigneeIntel Corporation
InventorsNicole Meier Chang, George J. Korsh, Shafqat Ahmed, John Nugent, Ed Nabighian
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Abstract
An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
Claims6
A semiconductor apparatus, comprising:
- an active die region;
- a guard ring having a plurality of stacked metal layers, the plurality of stacked metal layers including a top metal layer, the guard ring having an area with an inner boundary closer to the active die region and an outer boundary further from the active die region;
- a first dielectric layer having a top boundary and a bottom boundary, at least some of the top metal layer being between the top and bottom boundaries of the first dielectric layer;
- a passivation layer over at least a portion of the top metal layer and at least a portion of the first dielectric layer;
- a trench in the passivation layer extending to at least the level of a top surface of the top metal layer of the guard ring, the trench being further from the active die than the inner boundary of the guard ring area;
- and
- a material comprising a metal in the trench, at least some of the material comprising a metal being above the top boundary of the first dielectric layer.
4 more elements
Dependencies are inferred from the claim text.