# US 2010/0169846 A1 · Methods for gate-length biasing using annotation data

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- Number: US 2010/0169846 A1
- Document ID: US20100169846A1
- Status: Published application
- Kind: A1
- Application number: 12/717,885
- Filed: 2010-03-04
- Published: 2010-07-01
- Earliest claimed: 2008-09-17
- Assignees: Tela Innovations. Inc., a Delaware Corporation
- Inventors: Puneet Gupta; Andrew B. Kahng
- Web page: https://patentgrep.com/patent/US20100169846A1

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/36: Circuit design at the analogue level
- G06F 30/373: Design optimisation
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- H10D 84/907: {CMOS gate arrays}
- H10D 89/10: Integrated device layouts
- G06F 2119/06: Power analysis or power optimisation
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout.

## Claims

### Claim 1

A method for generating a biased layout for making an integrated circuit, comprising:
(a) obtaining a nominal layout defined by one or more cells, each cell having one or more transistor gate features with a nominal gate length;
(b) obtaining an annotated layout, the annotated layout containing information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout; and
(c) producing a biased layout by modifying the nominal layout using the information from the annotated layout, such that the biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout.

### Claim 2 (depends on 1)

The method of claim 1, wherein the biased layout includes cells with transistors that have modifications to gate length and cells that do not have modifications to gate length.

### Claim 3 (depends on 1)

The method of claim 1, wherein the annotated layout contains information indicating at least two gate length sizes that are different than the nominal gate length.

### Claim 4 (depends on 1)

The method of claim 1, wherein producing the biased layout is executed by an electronic design automation (EDA) tool.

### Claim 5 (depends on 1)

The method of claim 1, wherein the information contained in the annotation layout includes gate-length biasing that is pre-qualified as safe by a particular foundry.

### Claim 6 (depends on 1)

The method of claim 1, wherein transistors identified for gate length biasing are on non-critical timing paths.

### Claim 7 (depends on 1)

The method of claim 1, wherein producing the biased layout is executed through one of an EDA tool, a design rule checker (DRC) tool, an optical proximity correction (OPC) tool, or a combination thereof.

### Claim 8 (depends on 1)

The method of claim 1, wherein an optimizer receives inputs for identifying which of the cells in the nominal layout include transistors to be biased for producing the annotated layout.

### Claim 9 (depends on 8)

The method of claim 8, wherein the inputs include one or more of a set of characteristic models, a set of design constraints, the nominal layout, and a design netlist.

### Claim 10 (depends on 8)

The method of claim 8, wherein the characteristic models include a timing library.

### Claim 11 (depends on 9)

The method of claim 9, wherein the set of design constraints include one or more of timing, power and yield.

### Claim 12 (depends on 1)

The method of claim 1, wherein the annotated layout further defines shape or size parameters for biasing particular ones of the transistors.

### Claim 13 (depends on 1)

The method of claim 1, wherein the gate-length biasing length is a predefined fraction of the nominal gate-length.

### Claim 14 (depends on 13)

The method of claim 13, wherein the predefined fraction is equal to 10% of the nominal gate length.

### Claim 15 (depends on 1)

The method of claim 1, wherein producing the biased layout is performed based on a predefined goal including at least one of a tradeoff between reducing leakage power, or reducing impact on timing delays for the integrated digital circuit.

### Claim 16 (depends on 1)

The method of claim 1, wherein the physical verification is performed before or after gate-length biasing.

### Claim 17 (depends on 16)

The method of claim 16, wherein the physical verification ensures meeting a predefined set of design rules.

### Claim 18 (depends on 1)

The method of claim 1, wherein the gate-length biasing defines an increase or decrease in the gate length of a selected transistor gate feature.

### Claim 19 (depends on 1)

The method in claim 1, wherein the annotated layout identifies transistors with at least two threshold voltages.

### Claim 20 (depends on 1)

The method in claim 1, wherein all transistors in at least one cell are identified in the annotated layout for gate length biasing.