# US 2010/0169752 A1 · Storage circuit with fault detection and method for operating the same

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- Number: US 2010/0169752 A1
- Document ID: US20100169752A1
- Status: Published application
- Kind: A1
- Application number: 12/344,916
- Filed: 2008-12-29
- Published: 2010-07-01
- Earliest claimed: 2008-12-29
- Assignees: Infineon Technologies AG
- Inventors: THOMAS KUENEMUND
- Web page: https://patentgrep.com/patent/US20100169752A1

## CPC

- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state. Furthermore the storage circuit comprises a data input, a circuitry configured to cause the first fault detection circuit to assume the first stable state and the second fault detection circuit to assume the second stable state to store a data signal applied to the data input and a first output indicative of the state of the first fault detection circuit and a second output indicative of the state of the second fault detection circuit, wherein an invalid combination of the signal states at the first and second outputs indicate a fault.

## Claims

### Claim 1

A storage circuit with fault detection, comprising:
first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state;
a data input;
a circuitry configured to cause the first fault detection circuit to assume the first stable state and the second fault detection circuit to assume the second stable state to store a data signal applied to the data input; and
a first output indicative of the state of the first fault detection circuit and a second output indicative of the state of the second fault detection circuit, wherein an invalid combination of the signal states at the first and second outputs indicates a fault.

### Claim 2 (depends on 1)

The storage circuit with fault detection according to claim 1, further comprising an enable input, wherein the circuitry is configured to allow storage of a data signal applied to the data input if an enable signal is applied to the enable input and to prevent storage of the data signal applied to the data input if the enable signal is not applied to the enable input.

### Claim 3 (depends on 1)

The storage circuit with fault detection according to claim 1, wherein the first fault detection circuit comprises a first reset-set latch and wherein the second fault detection circuit comprises a second reset-set latch.

### Claim 4 (depends on 3)

The storage circuit according to claim 3, wherein the circuitry comprises a first inverter coupling an output of the first reset-set latch to a set input of the second reset-set latch and a second inverter coupling an output of the second reset-set latch to a set input of the first reset-set latch.

### Claim 5 (depends on 3)

The storage circuit with fault detection according to claim 3, wherein the circuitry is configured to apply a reset signal to a reset input of the first reset-set latch and not apply a reset signal to a reset input of the second reset-set latch if a data signal having a first signal state is applied to the data input, and is configured to apply a reset signal to the reset input of the second reset-set latch and not apply a reset signal to the reset input of the first reset-set latch if a data signal having a second signal state is applied to the data input.

### Claim 6 (depends on 5)

The storage circuit with fault detection according to claim 5, further comprising an enable input, wherein the circuitry is configured to apply the respective reset signals only when an enable signal is applied to the enable input.

### Claim 7 (depends on 6)

The storage circuit for fault detection according to claim 6, wherein the circuitry comprises a first logic circuit configured to provide the reset signal for the first reset-set latch and a second logic circuit configured to provide the reset signal for the second reset-set latch.

### Claim 8 (depends on 7)

The storage circuit with fault detection according to claim 7, wherein the first logic circuit comprises a first NOR-gate and an inverter, wherein the inverter is coupled between the data input and a first input of the first NOR-gate, wherein the second input of the first NOR-gate is coupled to the enable input and wherein an output of the first NOR-gate is coupled to the reset input of the first reset-set latch, and
wherein the second logic circuit comprises a second NOR-gate, wherein a first input of the second NOR-gate is coupled to the data input, a second input of the second NOR-gate is coupled to the enable input and the output of the second NOR-gate is coupled to the reset input of the second reset-set latch.

### Claim 9 (depends on 7)

The storage circuit with fault detection according to claim 7, wherein the first logic circuit comprises a first AND-gate, wherein a first input of the first AND-gate is coupled to the data input, wherein a second input of the first AND-gate is coupled to the enable input and wherein an output of the AND-gate is coupled to the reset input of the first reset-set latch;
the second logic circuit comprises a second AND-gate and an inverter, wherein the inverter is coupled between a first input of the second AND-gate and the data input, wherein the second input of the AND-gate is coupled to the enable input and wherein the output of the AND-gate is coupled to the reset input of the second reset-set latch.

### Claim 10 (depends on 7)

The storage circuit with fault detection according to claim 7, further comprising a third logic circuit configured to output an alarm signal if signals, which, depending on the signal states at the first and second outputs, indicate an invalid combination of signal states at the outputs.

### Claim 11 (depends on 10)

The storage circuit with fault detection according to claim 10, wherein the third logic circuit is formed in a semiconductor substrate physically adjacent to the first and second logic circuits or between the first and second logic circuits.

### Claim 12 (depends on 10)

The storage circuit with fault detection according to claim 10, wherein each of the first, second and third logic circuits comprise transistors of different doping types, wherein in the first and second logic circuits, transistors of a first doping type are dimensioned to obtain a higher current yield than transistors of a second doping type, and, in the third logic circuit, transistors of the second doping type are dimensioned to obtain a higher current rate than transistors of the first doping type.

### Claim 13 (depends on 11)

The storage circuit according to claim 11, wherein the semiconductor substrate comprises p- and n-type doped regions, and wherein the first, the second and the third logic circuits are arranged neighboring to potential terminals of the p- and/or n-type doped regions in the semiconductor substrate.

### Claim 14 (depends on 1)

A memory device, comprising:
a memory controller;
a plurality of storage circuits with fault detection according to claim 1;
wherein each storage circuit comprises an address, and wherein the memory controller is configured to control storing of data into the storage circuit, and reading of data from the storage circuit; and
a monitor circuit configured to monitor an indication of a fault.

### Claim 15 (depends on 14)

The memory device according to claim 14, wherein each of the plurality of storage circuits with fault detection further comprise an enable input, wherein the circuitry is configured to allow storage of a data signal applied to the data input if an enable signal is applied from the memory controller to the enable input and to prevent storage of the data signal applied to the data input if the enable signal from the memory controller is not applied to the enable input.

### Claim 16 (depends on 14)

The memory device according to claim 14, wherein the circuitry of each of the plurality of storage circuits with fault detection is configured to output an alarm signal if signal states at the first and second outputs indicate a fault.

### Claim 17

A storage circuit with fault detection, comprising:
a data input;
an enable input;
first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state, wherein the first fault detection circuit comprises a reset input, a set input and at least a first output, wherein the second fault detection circuit comprises a reset input, a set input and at least a second output, and wherein the first output is coupled to the set input of the second fault detection circuit and the second output is coupled to the set input of the first fault detection circuit;
a first logic circuit configured to provide a reset signal to the reset input of the first fault detection circuit, and
a second logic circuit configured to provide a reset signal to the reset input of the second fault detection circuit,
wherein the first and the second logic circuits are configured to allow storing of a data signal applied to the data input if an enable signal is applied to the enable input and to prevent storage of the data signal applied to the data input if the enable signal is not applied to the enable input, and
wherein the first output is indicative of the state of the first fault detection circuit and the second output is indicative of the state of the second fault detection circuit, wherein an invalid combination of the signal states at the first and second outputs indicates a fault.

### Claim 18 (depends on 17)

The storage circuit with fault detection according to claim 17, further comprising a first inverter coupled between the first output of the first fault detection circuit and the set input of the second fault detection circuit and a second inverter coupled between the second output of the second detection circuit and the set input of the first fault detection circuit.

### Claim 19 (depends on 17)

The storage circuit with fault detection according to claim 17, wherein the first fault detection circuit comprises a first reset-set latch and wherein the second fault detection circuit comprises a second reset-set latch.

### Claim 20 (depends on 17)

The storage circuit with fault detection according to claim 17, wherein the first logic circuit comprises a first NOR-gate and an inverter, wherein the inverter is coupled between the data input and a first input of the first NOR-gate, wherein the second input of the first NOR-gate is coupled to the enable input and wherein an output of the first NOR-gate is coupled to the reset input of the first reset-set latch, and wherein the second logic circuit comprises a second NOR-gate, wherein a first input of the second NOR-gate is coupled to the data input, a second input of the second NOR-gate is coupled to the enable input and the output of the second NOR-gate is coupled to the reset input of the second reset-set latch.

### Claim 21

A storage circuit with fault detection, comprising:
a master-latch comprising:
a data input;
an enable input;
a first and a second master-latch output;
first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state, wherein the first fault detection circuit comprises a reset input, a set input and a first output forming the first master-latch output, and wherein the second fault detection circuit comprises a reset input, a set input and a second output forming the second master-latch output;
a first logic circuit having inputs coupled to the data input and the enable input and an output coupled to the reset input of the first fault detection circuit; and
a second logic circuit having inputs coupled to the data input and the enable input and an output coupled to the reset input of the second fault detection circuit; and
a slave-latch comprising:
a first and a second data input;
an enable input;
a first and a second slave-latch output;
first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state, wherein the first fault detection circuit comprises a reset input, a set input and a first output forming the first slave-latch output, and wherein the second fault detection circuit comprises a reset input, a set input and at least a second output forming a second slave-latch output;
a first logic circuit having an input coupled to the first data input of the slave-latch and a second input coupled to the enable input of the slave-latch and an output coupled to the reset input of the first fault detection circuit at the slave-latch; and
a second logic circuit having an input coupled to the second data input and a second input coupled to the enable input of the slave-latch and an output coupled to the reset input of the second fault detection circuit of the slave-latch;
wherein the first master-latch output is coupled to the first data input of the slave-latch and the second master-latch output is coupled to the second data input of the slave-latch, and wherein the enable input of the master-latch is adapted to receive an enable signal and wherein the enable input of the slave-latch is adapted to receive an inverted version of the enable signal.

### Claim 22

A method for operating a storage circuit with fault detection, wherein the storage circuit comprises a data input, an enable input, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state, a first output of the first fault detection circuit indicative of the state of the first fault detection circuit and a second output indicative of the state of the second fault detection circuit, the method comprising:
applying a data signal to the data input to bring the first fault detection circuit into the first stable state and the second fault detection circuit into the second stable state; and
monitoring signal states at the first output of the first fault detection circuit and at the second output of the second fault detection circuit,
wherein an invalid logic combination of the signal states at the first and second outputs indicates a fault and a valid logic combination of the signal states at the first and second outputs indicates valid stored data.

### Claim 23 (depends on 22)

The method according to claim 22, further comprising logically combining the signal states at the first and second outputs and outputting an alarm signal if an invalid logic combination at the first and the second outputs indicates a fault.

### Claim 24 (depends on 23)

The method according to claim 23, further comprising applying an enable signal to an enable input of the first and second fault detection circuits, wherein the states of the first and second fault detection circuits can be changed by applying a data signal to the data input, when the enable signal is applied.

### Claim 25

A storage circuit with fault detection, comprising:
first and second fault detection means for detecting a fault, each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection means is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state;
a data input;
means for causing the first fault detection means to assume the first stable state and the second fault detection means to assume the second stable state to store a data signal applied to the data input; and
a first output indicative of the state of the first fault detection means and a second output indicative of the state of the second fault detection means, wherein an invalid combination of the signal states at the first and second outputs indicates a fault.