# US 2010/0169740 A1 · Accelerating phase change memory writes

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- Number: US 2010/0169740 A1
- Document ID: US20100169740A1
- Status: Published application
- Kind: A1
- Application number: 12/346,697
- Filed: 2008-12-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Assignees: STMicroelectronics S.r.I.
- Inventors: Meenatchi Jagasivamani; Anthony Ko; Rich E. Fackenthal; Ferdinando Bedeschi; Enzo Donze; Ravi Gutala
- Web page: https://patentgrep.com/patent/US20100169740A1

## CPC

- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.

## Claims

### Claim 1

A method comprising:
writing to a phase change memory using a software control; and accelerating the writing to the phase change memory using a hardware accelerator.

### Claim 2 (depends on 1)

The method of claim 1 wherein using a hardware accelerator includes detecting a change in set current.

### Claim 3 (depends on 2)

The method of claim 2 including detecting a reduction in set current.

### Claim 4 (depends on 2)

The method of claim 2 wherein detecting a change in set current includes causing a signal to change state in response to the detection of said change of said set current.

### Claim 5 (depends on 4)

The method of claim 4 including generating a signal to end a programming cycle in response to the detection of said change in set current.

### Claim 6 (depends on 5)

The method of claim 5 including using both the rising and falling edges of said signal generated in response to the detection of the change of the set current.

### Claim 7 (depends on 6)

The method of claim 6 including generating an address to a phase change memory array in response to the detection of the reduction of set current.

### Claim 8 (depends on 7)

The method of claim 7 including using an address counter to automatically update the address to be programmed.

### Claim 9 (depends on 1)

The method of claim 1, including locating errors at bits of the phase change memory array and selectively modifying bits at which errors have been located.

### Claim 10 (depends on 9)

The method of claim 9, wherein locating errors includes using an error correction code.

### Claim 11 (depends on 10)

The method of claim 10, wherein locating errors includes reading a memory word from a memory location, using the error correction code to generate a correction signature for at least a portion of the memory word, generating a corrected word from the memory word and from the correction signature and comparing the corrected word with the memory word.

### Claim 12 (depends on 11)

The method of claim 11, comprising generating a correction mask from the comparing the corrected word with the memory word.

### Claim 13 (depends on 9)

The method of claim 9, wherein selectively modifying comprises applying program pulses selectively to the bits at which errors have been located.

### Claim 14

A phase change memory comprising:
a memory array including phase change memory cells; and
a hardware accelerator configured to accelerate writing data to the phase change memory array.

### Claim 15 (depends on 14)

The memory of claim 14 wherein said hardware accelerator includes a detector to detect a change in set current.

### Claim 16 (depends on 15)

The memory of claim 15 wherein said detector is an edge detector.

### Claim 17 (depends on 15)

The memory of claim 15 wherein said detector to detect a change in set current and to cause a signal to change state in response to the detection of change of set current.

### Claim 18 (depends on 17)

The memory of claim 17, said detector to generate a signal to end a programming cycle in response to the detection of said change in set current.

### Claim 19 (depends on 18)

The memory of claim 18 including a pulse synchronizer to generate said signal.

### Claim 20 (depends on 19)

The memory of claim 19 wherein said edge detector to use both the rising and falling edges of said signal generated in response to the detection of the change in set current.

### Claim 21 (depends on 20)

The memory of claim 20 including an address counter to generate an address to said phase change memory array in response to the detection of the reduction of set current.

### Claim 22 (depends on 21)

The memory of claim 21 wherein said address counter to automatically update the address to be programmed in the memory array.

### Claim 23 (depends on 14)

The memory of claim 14, comprising an error correction module to locate errors at bits of said memory array and a control to selectively modify bits at which errors have been located.

### Claim 24 (depends on 23)

The memory of claim 23, wherein said error correction module to use an error correction code.

### Claim 25 (depends on 24)

The memory of claim 24, wherein said error correction to receive a memory word from a memory location, to use said error correction code to generate a correction signature for at least a portion of said memory word, to generate a corrected word from said memory word and from said correction signature and to compare said corrected word with said memory word.

### Claim 26 (depends on 25)

The method of claim 25, wherein the control to apply program pulses selectively to the bits at which errors have been located.

### Claim 27

A system comprising:
a processor; and
a phase change memory coupled to said processor, said phase change memory including a memory array including phase change memory cells and a hardware accelerator to accelerate writing data to said phase change memory array.

### Claim 28 (depends on 27)

The system of claim 27 wherein said hardware accelerator includes a detector to detect a change in set current.

### Claim 29 (depends on 28)

The system of claim 28 wherein said detector is an edge detector.

### Claim 30 (depends on 28)

The system of claim 28 wherein said detector to detect a change in set current and to cause a signal to change state in response to the detection of change of set current.

### Claim 31 (depends on 30)

The system of claim 30, said detector to generate a signal to end a programming cycle in response to the detection of said change in set current.

### Claim 32 (depends on 31)

The system of claim 31 including a pulse synchronizer to generate said signal.

### Claim 33 (depends on 32)

The system of claim 32 wherein said edge detector to use both the rising and falling edges of said signal generated in response to the detection of the change in set current.

### Claim 34 (depends on 33)

The system of claim 33 including an address counter to generate an address to said phase change memory array in response to the detection of the reduction of set current.

### Claim 35 (depends on 27)

The system of claim 27, wherein said phase change memory includes an error correction module to locate errors at bits of said memory array and a control to selectively modify bits at which errors have been located.

### Claim 36 (depends on 35)

The system of claim 35, wherein the error correction module to use an Error Correction Code.

### Claim 37 (depends on 36)

The system of claim 36, wherein the error correction to receive a memory word from a memory location, to use the error correction code to generate a correction signature for at least a portion of the memory word, to generate a corrected word from the memory word and from the correction signature and to compare the corrected word with the memory word.

### Claim 38 (depends on 37)

The method of claim 37, wherein the control to apply program pulses selectively to the bits at which errors have been located.