# US 2010/0169735 A1 · Low density parity check code row update instruction

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- Number: US 2010/0169735 A1
- Document ID: US20100169735A1
- Status: Published application
- Kind: A1
- Application number: 12/347,731
- Filed: 2008-12-31
- Published: 2010-07-01
- Earliest claimed: 2008-12-31
- Assignees: Texas Instruments Incorporated
- Inventors: Eric BISCONDI; David J. HOYLE; Tod D. WOLF
- Web page: https://patentgrep.com/patent/US20100169735A1

## CPC

- H03M 13/1117: {using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule}
- H03M 13/6502: {Reduction of hardware complexity or efficient processing}
- H03M 13/6544: {IEEE 802.16 (WIMAX and broadband wireless access)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Apparatus for optimizing low-density parity check (“LDPC”) decoding in a processor is disclosed herein. A processor in accordance with the present disclosure includes an LDPC decoder row update execution unit. The LDPC decoder row update execution unit accelerates an LDPC row update computation by performing a logarithm estimation and a magnitude minimization in parallel. The execution unit is activated by execution of an LDPC row update instruction. The execution unit adds a minimum of magnitudes of two input values to a difference of estimated logarithms of exponential functions of a sum and a difference of the two input values to produce a row update value.

## Claims

### Claim 1

A processor, comprising:
a low density parity check (“LDPC”) decoder row update execution unit that accelerates an LDPC row update computation by performing a logarithm estimation and a magnitude minimization in parallel.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the execution unit is activated by execution of an LDPC row update instruction.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the execution unit comprises logic that determines an absolute value of an input value.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the execution unit comprises logic that determines a minimum of absolute values of two input values.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the execution unit comprises an adder that computes the sum of two input values, and a subtractor that computes the difference of the two input values.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the execution unit comprises logic that estimates log(1+e−|z|) where z is the sum of two input values and the difference of the two input values.

### Claim 7 (depends on 1)

The processor of claim 1, wherein the execution unit adds the minimum of magnitudes of two input values to a difference of estimated logarithms of exponential functions of a sum and a difference of the two input values.

### Claim 8 (depends on 1)

The processor of claim 1, wherein the execution unit operates on signed input values.

### Claim 9 (depends on 1)

The processor of claim 1, wherein the execution unit operates on unsigned input values..

### Claim 10 (depends on 1)

The processor of claim 1, further comprising a plurality of said execution units; wherein a plurality of LDPC row update values are computed for each row update instruction executed.

### Claim 11

A system, comprising:
a receiver that comprises:
a processor based low density parity check (“LDPC”) decoder;
wherein the processor executes an LDPC row update instruction that causes the processor to compute, at least a portion of, a check node update value.

### Claim 12 (depends on 11)

The system of claim 11, wherein the processor comprises a check node update execution unit that is invoked by execution of the row update instruction.

### Claim 13 (depends on 11)

The system of claim 11, wherein the processor adds a minimum of absolute values of two input values and a difference of estimated logarithms of exponential functions of a sum and difference of the two input values while executing the row update instruction.

### Claim 14 (depends on 11)

The system of claim 11, wherein the processor comprises a plurality of check node update execution units that are invoked by execution of the row update instruction and computes a plurality of check node update values in parallel.

### Claim 15 (depends on 11)

The system of claim 11, wherein the processor takes two previously computed magnitude values as operands for the row update instruction.

### Claim 16 (depends on 11)

The system of claim 11, further comprising a transmitter that LDPC encodes data transmitted to the receiver.

### Claim 17

A low density parity check (“LDPC”) code decoder, comprising:
a processor that comprises an LDPC check node update execution unit that computes, at least a portion of, a check node update value.

### Claim 18 (depends on 17)

The LDPC decoder of claim 17, wherein the processor executes an LDPC check node update instruction that causes the check node update execution unit to compute the check node update value.

### Claim 19 (depends on 17)

The LDPC decoder of claim 17, wherein the processor comprises a plurality of check node execution units that compute a plurality of check node update values in parallel when the processor executes a row update instruction.

### Claim 20 (depends on 17)

The LDPC decoder of claim 17, wherein the check node execution unit sums a minimum magnitude of two input values with a difference of estimated logarithms of exponential functions of a sum and difference of the two input values to generate the check node update value.

### Claim 21

A method, comprising:
decoding a low density parity check (“LDPC”) code row update instruction in a processor; and
instructing an LDPC row update execution unit in the processor to compute, at least a portion, of an LDPC row update value.

### Claim 22 (depends on 21)

The method of claim 21, further comprising decoding an LDPC code row update instruction that directs the execution unit to compute LDPC row update values for a plurality of rows in parallel.

### Claim 23 (depends on 21)

The method of claim 21, further comprising computing, in parallel, row update values for a plurality of LDPC rows in the execution unit.

### Claim 24 (depends on 21)

The method of claim 21, further comprising computing, in the LDPC row update execution unit, a minimum magnitude of a pair of input values provided to the execution unit.

### Claim 25 (depends on 21)

The method of claim 21, further comprising adding, in the LDPC row update execution unit, a minimum magnitude of two input values to a difference of estimated logarithms of exponential functions of a sum and difference of the two input values.