# US 2010/0169730 A1 · Phase error detection device, phase error detecting method, integrated circuit and optical disc device

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- Number: US 2010/0169730 A1
- Document ID: US20100169730A1
- Status: Published application
- Kind: A1
- Application number: 12/640,218
- Filed: 2009-12-17
- Published: 2010-07-01
- Earliest claimed: 2008-12-25
- Assignees: Panasonic Corporation
- Inventors: Naohiro KIMURA
- Web page: https://patentgrep.com/patent/US20100169730A1

## CPC

- G11B 20/10009: {Improvement or modification of read or write signals}
- G11B 20/10037: {A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof}
- G11B 20/10046: {filtering or equalising, e.g. setting the tap weights of an FIR filter}
- G11B 20/1012: {partial response PR(1,2,2,2,1)}
- G11B 20/10212: {compensation for data shift, e.g. pulse-crowding effects}
- G11B 20/10222: {clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation (dedicated sync patterns in the modulation code G11B20/1403)}
- G11B 20/10425: {by counting out-of-lock events of a PLL}
- G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R)

## Abstract

A phase error detection device detects a phase error, based on an output from an A/D conversion section that performs A/D conversion on an analog input signal in accordance with a sampling clock to generate a digital reproduction signal. The phase error detection device includes a phase error generation section that generates the phase error from the output from the A/D conversion section, and a phase error correction section that corrects the phase error. Herein, the phase error correction section determines a phase error detection range from past phase errors and, when the phase error generated by the phase error generation section is out of the phase error detection range, corrects the phase error.

## Claims

### Claim 1

A phase error detection device for detecting a phase error, based on an output from an A/D conversion section that performs A/D conversion on an analog input signal in accordance with a sampling clock to generate a digital reproduction signal,
said phase error detection device comprising:
a phase error generation section that generates the phase error from the output from the A/D conversion section; and
a phase error correction section that corrects the phase error, wherein:
said phase error correction section determines a phase error detection range from past phase errors and, when the phase error generated by the phase error generation section is out of the phase error detection range, corrects the phase error.

### Claim 2 (depends on 1)

The phase error detection device according to claim 1, wherein:
said phase error correction section corrects the phase error generated by the phase error generation section by inverting a sign of the phase error.

### Claim 3 (depends on 1)

The phase error detection device according to claim 1, wherein:
said phase error correction section corrects the phase error generated by the phase error generation section to generate a value which is opposite in polarity to a sign of the phase error and has a predetermined degree.

### Claim 4 (depends on 1)

The phase error detection device according to claim 1, wherein:
said phase error correction section corrects the phase error generated by the phase error generation section to generate a value obtained by adding, to the phase error, a value which is opposite in polarity to the phase error and has a degree of 360°.

### Claim 5 (depends on 1)

The phase error detection device according to claim 1, wherein:
said phase error correction section determines the phase error detection range from an average value of the predetermined number of past phase errors.

### Claim 6 (depends on 1)

The phase error detection device according to claim 1, wherein:
said phase error correction section determines a center of the phase error detection range from an approximate straight line obtained from three or more past phase errors.

### Claim 7 (depends on 1)

The phase error detection device according to claim 1, wherein:
the phase error detection range determined by said phase error correction section has at least an upper limit or a lower limit set therefor.

### Claim 8 (depends on 1)

The phase error detection device according to claim 1, wherein:
the phase error generation section includes:
an equalization section that equalizes the digital reproduction signal to generate an equalization signal having a predetermined equalization characteristic;
a binarization section that binarizes the equalization signal to generate a binarization signal; and
a computing section that computes the phase error, and
the computing section includes:
a difference metric computing section that generates an ideal reproduction signal from the binarization signal, based on the equalization characteristic, calculates a first metric between the equalization signal and the ideal reproduction signal, generates an ideal comparison signal from a comparison signal obtained by shifting a rising or falling edge of the binarization signal by one time, based on the equalization characteristic, calculates a second metric between the equalization signal and the ideal comparison signal, and computes a difference metric between the first metric and the second metric;
a distance computing section that calculates a square of a Euclidean distance between the ideal reproduction signal and the ideal comparison signal; and
a phase error computing section that calculates a phase error from a difference between the difference metric and the square of the Euclidean distance.

### Claim 9 (depends on 8)

The phase error detection device according to claim 8, wherein:
said phase error correction section corrects the phase error when the difference metric is equal to or less than the square of the Euclidean distance between the ideal reproduction signal and the ideal comparison signal, and makes the phase error invalid when the difference metric is larger than the square of the Euclidean distance between the ideal reproduction signal and the ideal comparison signal.

### Claim 10 (depends on 8)

The phase error detection device according to claim 8, wherein:
said phase error correction section corrects the phase error generated by the phase error generation section by correcting the binarization signal to regenerate the phase error.

### Claim 11 (depends on 8)

The phase error detection device according to claim 8, wherein:
said phase error correction section corrects the phase error generated by the phase error generation section by inverting a sign of the difference metric to regenerate the phase error.

### Claim 12

A phase error detecting method for detecting a phase error, based on an output from an A/D conversion section that performs A/D conversion on an analog input signal in accordance with a sampling clock to generate a digital reproduction signal,
the phase error detecting method comprising:
a phase error generating step of generating the phase error from the output from the A/D conversion section; and
a phase error correcting step of correcting the phase error, wherein:
in said phase error correcting step a phase error detection range is determined from past phase errors and the phase error is corrected when the phase error generated in the phase error generating step is out of the phase error detection range.

### Claim 13

An integrated circuit comprising:
an A/D conversion section that performs A/D conversion on an analog input signal in accordance with a sampling clock to generate a digital reproduction signal;
a phase error generation section that generates a phase error from the output from the A/D conversion section; and
a phase error correction section that corrects the phase error, wherein:
said phase error correction section determines a phase error detection range from past phase errors and, when the phase error generated by the phase error generation section is out of the phase error detection range, corrects the phase error.

### Claim 14 (depends on 1)

An optical disc device comprising:
an optical head section that reads out information from an optical disc to generate an analog reproduction signal; and
a PLL section that generates a sampling clock brought into phase synchronization with the analog reproduction signal, wherein:
the PLL section includes the phase error detection device according to claim 1.