# US 2010/0169729 A1 · Enabling an integrated memory controller to transparently work with defective memory devices

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- Number: US 2010/0169729 A1
- Document ID: US20100169729A1
- Status: Published application
- Kind: A1
- Application number: 12/345,948
- Filed: 2008-12-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Inventors: SHAMANNA M. DATTA; JAMES W. ALEXANDER; MAHESH S. NATU; RAHUL KHANNA; MOHAN J. KUMAR
- Web page: https://patentgrep.com/patent/US20100169729A1

## CPC

- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/46: Test trigger logic
- G11C 29/50016: {of retention}
- G11C 29/76: {using address translation or modifications}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G11C 2029/5002: {Characteristic}
- G11C 2029/5004: {Voltage}
- G11C 2029/5606: {Error catch memory}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for enabling an integrated memory controller to transparently work with defective memory devices. In some embodiments, a marginal condition is imposed on a memory module during normal operations of the memory module. The term “marginal condition” refers to a condition that is out of compliance with a specified (or “normal”) operating condition for the memory module. The memory module may exhibit failures in response to the marginal conditions and compensating mechanisms may mitigate the failures.

## Claims

### Claim 1

An integrated circuit comprising:
a first logic to impose a marginal condition on a memory module during normal operation of the memory module, wherein the memory module is to be coupled with the first logic; and
a second logic to compensate for the marginal condition imposed on the memory module.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the marginal condition is a marginal operating voltage.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the marginal condition is a marginal operating temperature.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the marginal condition is a marginal refresh rate.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, wherein the second logic is logic to compensate for the marginal refresh rate.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein the second logic includes hard error detection logic to detect a hard error associated with a memory location on the memory module.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, wherein the second logic further includes relocation logic to relocate data away from the memory location.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, further comprising:
error correction logic coupled with the second logic, the error correction logic to detect errors in information stored on the memory module.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, further comprising:
one or more processor cores.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, further comprising:
a memory controller to control the transfer of information with the memory module.

### Claim 11

A method comprising:
initializing a computing system;
imposing a marginal condition on a memory module during normal operation of the memory module; and
compensating for the marginal condition imposed on the memory module.

### Claim 12 (depends on 11)

The method of claim 11, wherein the marginal condition is a marginal operating voltage.

### Claim 13 (depends on 11)

The method of claim 11, wherein the marginal condition is a marginal operating temperature.

### Claim 14 (depends on 11)

The method of claim 11, wherein the marginal condition is a marginal refresh rate.

### Claim 15 (depends on 14)

The method of claim 14, wherein compensating for the marginal condition imposed on the memory module comprises:
detecting a hard error associated with a memory location on the memory module.

### Claim 16 (depends on 15)

The method of claim 15, wherein detecting a hard error associated with a memory location on the memory module comprises:
detecting an error in information read from the memory location using error correction logic; and
determining whether the detected error is a hard error or a soft error.

### Claim 17 (depends on 16)

The method of claim 16, wherein determining whether the detected error is a hard error or a soft error comprises:
determining whether the error is persistent.

### Claim 18 (depends on 15)

The method of claim 15, wherein compensating for the marginal condition imposed on the memory module further comprises:
relocating information from the memory location to another memory location.

### Claim 19

A system comprising:
a memory module to provide at least a portion of main memory for a computing system; and
an integrated circuit coupled with the memory module via a memory interconnect, the integrated circuit including
a first logic to impose a marginal condition on the memory module during normal operation of the memory module, and
a second logic to compensate for the marginal condition imposed on the memory module.

### Claim 20 (depends on 19)

The system of claim 19, wherein the marginal condition is a marginal operating voltage.

### Claim 21 (depends on 19)

The system of claim 19, wherein the marginal condition is a marginal operating temperature.

### Claim 22 (depends on 19)

The system of claim 19, wherein the marginal condition is a marginal refresh rate.

### Claim 23 (depends on 22)

The system of claim 22, wherein the second logic is logic to compensate for the marginal refresh rate.

### Claim 24 (depends on 23)

The system of claim 23, wherein the second logic includes hard error detection logic to detect a hard error associated with a memory location on the memory module.

### Claim 25 (depends on 24)

The system of claim 24, wherein the second logic further includes relocation logic to relocate data away from the memory location.

### Claim 26 (depends on 25)

The system of claim 25, wherein the integrated circuit further comprises:
error correction logic coupled with the second logic, the error correction logic to detect errors in information stored on the memory module.

### Claim 27 (depends on 26)

The system of claim 26, wherein the integrated circuit further comprises:
one or more processor cores.

### Claim 28 (depends on 26)

The system of claim 26, wherein the integrated circuit further comprises:
a memory controller to control the transfer of information with the memory module.