# US 2010/0169728 A1 · Decoupled clocking in testing architecture and method of testing

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- Number: US 2010/0169728 A1
- Document ID: US20100169728A1
- Status: Published application
- Kind: A1
- Application number: 12/317,872
- Filed: 2008-12-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Assignees: Intel Corporation
- Inventors: David Dehnert; Matthew Heath
- Web page: https://patentgrep.com/patent/US20100169728A1

## CPC

- G01R 31/318555: {Control logic}
- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.

## Claims

### Claim 1

A test architecture comprising:
a first logic block having a plurality of first scan chains; and
a first scan controller including:
a first clock domain crossing circuit to process an exchange of an input test data packet and an output test data packet between the first scan controller and a test access mechanism which are operated by different clock sources,
a first decoding circuit to generate a first test stimulus from the input test data packet, and
a first input staging circuit and a first output staging circuit to process an exchange of the first test stimulus and a first test response between the first scan controller and the first scan chains of the first logic block.

### Claim 2 (depends on 1)

The test architecture of claim 1, wherein the scan controller and the test access mechanism are further operated in different clock frequencies.

### Claim 3 (depends on 1)

The test architecture of claim 1, further comprising:
a second clock domain crossing circuit disposed in the first logic block to process an exchange of the first test stimulus and the first test response between the first scan controller and the first scan chains of the first logic block.

### Claim 4 (depends on 1)

The test architecture of claim 1, wherein the first scan controller and the first scan chains are operated by different clock sources.

### Claim 5 (depends on 4)

The test architecture of claim 4, wherein the first scan controller and the first scan chains are further operated in different clock frequencies.

### Claim 6 (depends on 1)

The test architecture of claim 1, wherein the input test data packet and the first test stimulus have different bandwidths.

### Claim 7

A method of testing, comprising:
connecting a test access mechanism to a plurality of scan controllers which are coupled to a plurality of logic blocks having different scan chain designs;
deactivating a functional clock of a first of the logic blocks;
transmitting an input test data packet from the test access mechanism to a first of the scan controllers, wherein the test access mechanism and the first of the scan controllers are operated by different clock sources;
applying a first test stimulus, generated from the input test data packet, to the first of the logic blocks;
activating the functional clock of the first of the logic blocks for at least one clock cycle;
receiving a first test response from the first of the logic blocks; and
transmitting an output test data packet from the first of the scan controllers to the test access mechanism.

### Claim 8 (depends on 7)

The method of claim 7, wherein transmitting an input test data packet from the test access mechanism to a first of the scan controllers includes receiving the input test data packet at the first scan controller through a first clock domain crossing circuit.

### Claim 9 (depends on 8)

The method of claim 8, wherein applying a first test stimulus includes receiving the first test stimulus at the first of the logic blocks through a second clock domain crossing circuit.

### Claim 10 (depends on 7)

The method of claim 7, wherein transmitting an input test data packet includes transmitting the input test data packet to a second of the scan controllers, wherein the first and the second of the scan controllers are operated by different clock sources.

### Claim 11 (depends on 10)

The method of claim 10, wherein transmitting the input test data packet to a second of the scan controllers includes receiving the input test data packet at the second of the scan controllers through a third clock domain crossing circuit.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
applying a second test stimulus, generated from the input test data packet, to the second of the logic blocks, through a fourth clock domain crossing circuit.

### Claim 13 (depends on 7)

The method of claim 7, wherein transmitting an input test data packet includes having the test access mechanism and the first of the scan controllers operate in different clock frequencies.

### Claim 14 (depends on 7)

The method of claim 7, wherein transmitting an input test data packet includes having the first of the scan controllers and a plurality of scan chains of the first of the logic blocks operate by different clock sources.

### Claim 15 (depends on 7)

The method of claim 7, wherein transmitting an input test data packet includes transmitting the input test data packet having a first bandwidth, and applying a first test stimulus includes applying the first test stimulus having a second bandwidth which is different from the first bandwidth.