# US 2010/0169710 A1 · Delta checkpoints for a non-volatile memory indirection table

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- Number: US 2010/0169710 A1
- Document ID: US20100169710A1
- Status: Published application
- Kind: A1
- Application number: 12/345,997
- Filed: 2008-12-30
- Published: 2010-07-01
- Earliest claimed: 2008-12-30
- Assignees: Intel Corporation
- Inventors: Robert J. Royer, JR.; Richard Mangold
- Web page: https://patentgrep.com/patent/US20100169710A1

## CPC

- G06F 11/1441: {Resetting or repowering}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2212/7207: management of metadata or control data
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

According to some embodiments, delta checkpoints are provided for a non-volatile memory indirection table to facilitate a recovery process after a power loss event.

## Claims

### Claim 1

A method, comprising:
maintaining an indirection table associated with sized portions of a non-volatile memory, the indirection table including a mapping of logical-to-physical addresses; and
storing delta information in the non-volatile memory, the delta information being associated with updates to the indirection table in connection with a plurality of the sized portions of the non-volatile memory.

### Claim 2 (depends on 1)

The method of claim 1, wherein the non-volatile memory comprises a NAND memory.

### Claim 3 (depends on 2)

The method of claim 2, wherein the sized portions of the NAND memory comprise pages, each page including user data and metadata, and the plurality of pages comprise an erase block.

### Claim 4 (depends on 3)

The method of claim 3, wherein the delta information comprises a delta checkpoint page.

### Claim 5 (depends on 4)

The method of claim 4, wherein the delta checkpoint page includes (i) data for the delta checkpoint page and (ii) metadata for the delta checkpoint page.

### Claim 6 (depends on 5)

The method of claim 5, wherein the data for the delta checkpoint page includes a logical address for each page in the erase block.

### Claim 7 (depends on 6)

The method of claim 6, wherein the data for the delta checkpoint page further includes a bitmask of erased blocks.

### Claim 8 (depends on 5)

The method of claim 5, wherein the metadata for the delta checkpoint page includes a logical address identifying the page as a delta checkpoint page.

### Claim 9 (depends on 5)

The method of claim 5, wherein the metadata for the delta checkpoint page includes a master sequence number.

### Claim 10 (depends on 2)

The method of claim 2, wherein the sized portions of the NAND memory comprise pages, each page including user data, and the plurality of pages include a number of different erase blocks that represent a virtual erase block.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
after a power loss event, reading the delta information from the non-volatile memory;
re-creating the indirection based at least in part on delta information; and
arranging to recover a memory state associated with the non-volatile in accordance with the re-created indirection table.

### Claim 12

An apparatus, comprising:
an indirection table structure associated with sized portions of a non-volatile memory, the indirection table including a mapping of logical-to-physical addresses; and
a non-volatile memory to store delta information, the delta information being associated with updates to the indirection table in connection with a plurality of the sized portions of the non-volatile memory.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the non-volatile memory comprises a NAND memory, the sized portions of the NAND memory comprise pages, the plurality of pages comprise an erase block, and the delta information comprises a delta checkpoint page.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the delta checkpoint page includes: (i) data for the delta checkpoint page including a logical address for each page in the erase block, and (ii) metadata for the delta checkpoint page, including a logical address identifying the page as a delta checkpoint page and a master sequence number, and further wherein a delta checkpoint entry is to be invalidated when more than one erase block is written to at the same time.

### Claim 15 (depends on 13)

The apparatus of claim 13, further comprising:
a recovery apparatus to, after a power loss event:
read the delta information from the non-volatile memory,
re-create the indirection based at least in part on delta information, and
arrange to recovery a memory state associated with the non-volatile in accordance with the re-created indirection table.